#
# This software is Copyright (c) 2016 Denis Burykin
# [denis_burykin yahoo com], [denis-burykin2014 yandex ru]
# and it is hereby released to the general public under the following terms:
# Redistribution and use in source and binary forms, with or without
# modification, are permitted.
#
# TIMESPEC's moved to clocks.ucf
NET "IFCLK_IN"  LOC = "K20" |IOSTANDARD = LVCMOS33 ;
NET "FXCLK_IN"  LOC = "L22" | IOSTANDARD = LVCMOS33 ;

NET "CS_IN"  LOC = "AB11" |IOSTANDARD = LVCMOS33 ;

NET "PA0"  LOC = "AA22" |IOSTANDARD = LVCMOS33 ;
NET "PA1"  LOC = "W17" |IOSTANDARD = LVCMOS33 ;	
NET "PA7" LOC = "AB17" |IOSTANDARD = LVCMOS33 ;	

NET "SLOE"  LOC = "U15" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;		# PA2
NET "SLRD"  LOC = "N22" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
NET "SLWR"  LOC = "M22" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;
NET "PKTEND"  LOC = "AB5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ;	# PA6
NET "FIFOADR0"  LOC = "AB21" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;	# PA4
NET "FIFOADR1"  LOC = "Y18" |IOSTANDARD = LVCMOS33 |DRIVE = 12 ;	# PA5
NET "FLAGA"  LOC = "F20" |IOSTANDARD = LVCMOS33 ;
NET "FLAGB"  LOC = "F19" |IOSTANDARD = LVCMOS33 ;
NET "FLAGC"  LOC = "F18" |IOSTANDARD = LVCMOS33 ;

NET "FIFO_DATA<0>"  LOC = "Y17" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<1>"  LOC = "V13" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<2>"  LOC = "W13" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<3>"  LOC = "AA8" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<4>"  LOC = "AB8" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<5>"  LOC = "W6" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<6>"  LOC = "Y6" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<7>"  LOC = "Y9" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<8>"  LOC = "V21" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<9>"  LOC = "V22" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<10>"  LOC = "U20" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<11>"  LOC = "U22" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<12>"  LOC = "R20" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<13>"  LOC = "R22" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<14>"  LOC = "P18" |IOSTANDARD = LVCMOS33 ;
NET "FIFO_DATA<15>"  LOC = "P19" |IOSTANDARD = LVCMOS33 ;


NET "PC<0>" LOC="G20" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<1>" LOC="T20" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<2>" LOC="Y5" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<3>" LOC="AB9" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<4>" LOC="G19" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<5>" LOC="H20" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<6>" LOC="H19" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "PC<7>" LOC="H18" |IOSTANDARD = LVCMOS33 |DRIVE = 12;

NET "INT4" LOC = "C18" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
NET "INT5" LOC = "V17" |IOSTANDARD = LVCMOS33 |DRIVE = 12;
# NET "SCL" LOC = "F22" | IOSTANDARD = LVCMOS33 ;
# NET "SDA" LOC = "E22" | IOSTANDARD = LVCMOS33 ;
NET "FPGA_ID<0>" LOC="T12" |IOSTANDARD = LVCMOS33 ;
NET "FPGA_ID<1>" LOC="R13" |IOSTANDARD = LVCMOS33 ;
NET "FPGA_ID<2>" LOC="T14" |IOSTANDARD = LVCMOS33 ;

NET "FPGA_ID*" TIG;


# VCR
#AREA_GROUP "pblock_io3" RANGE=SLICE_X64Y84:SLICE_X71Y95;
#INST "vcr_inst" AREA_GROUP="pblock_io3";

