#
# This software is Copyright (c) 2018-2019 Denis Burykin
# [denis_burykin yahoo com], [denis-burykin2014 yandex ru]
# and it is hereby released to the general public under the following terms:
# Redistribution and use in source and binary forms, with or without
# modification, are permitted.
#


// ===========================================================
// Nodes - left side
AREA_GROUP "node1" RANGE=SLICE_X12Y34:SLICE_X19Y38;
INST "pkt_comm/bcast_net/node[1].r*" AREA_GROUP="node1";
INST "pkt_comm/units[0].unit_io_regs/stage[1].r*" AREA_GROUP="node1";
INST "pkt_comm/units[1].unit_io_regs/stage[1].r*" AREA_GROUP="node1";
INST "pkt_comm/units[5].unit_io_regs/stage[1].r*" AREA_GROUP="node1";
INST "pkt_comm/units[10].unit_io_regs/stage[1].r*" AREA_GROUP="node1";

AREA_GROUP "node2" RANGE=SLICE_X16Y64:SLICE_X23Y79;
INST "pkt_comm/bcast_net/node[2].r*" AREA_GROUP="node2";
INST "pkt_comm/units[0].unit_io_regs/stage[2].r*" AREA_GROUP="node2";
INST "pkt_comm/units[1].unit_io_regs/stage[2].r*" AREA_GROUP="node2";
INST "pkt_comm/units[10].unit_io_regs/stage[2].r*" AREA_GROUP="node2";

AREA_GROUP "node3" RANGE=SLICE_X10Y104:SLICE_X19Y105;
INST "pkt_comm/bcast_net/node[3].r*" AREA_GROUP="node3";
INST "pkt_comm/units[0].unit_io_regs/stage[3].r*" AREA_GROUP="node3";
INST "pkt_comm/units[1].unit_io_regs/stage[3].r*" AREA_GROUP="node3";

AREA_GROUP "node4" RANGE=SLICE_X14Y132:SLICE_X19Y140;
INST "pkt_comm/bcast_net/node[4].r*" AREA_GROUP="node4";
INST "pkt_comm/units[0].unit_io_regs/stage[4].r*" AREA_GROUP="node4";


AREA_GROUP "node7" RANGE=SLICE_X84Y32:SLICE_X85Y35;
INST "pkt_comm/bcast_net/node[7].r*" AREA_GROUP="node7";
INST "pkt_comm/units[2].unit_io_regs/stage[1].r*" AREA_GROUP="node7";
INST "pkt_comm/units[3].unit_io_regs/stage[1].r*" AREA_GROUP="node7";
INST "pkt_comm/units[7].unit_io_regs/stage[1].r*" AREA_GROUP="node7";
INST "pkt_comm/units[8].unit_io_regs/stage[1].r*" AREA_GROUP="node7";
INST "pkt_comm/units[9].unit_io_regs/stage[1].r*" AREA_GROUP="node7";
INST "pkt_comm/units[11].unit_io_regs/stage[1].r*" AREA_GROUP="node7";

AREA_GROUP "node8" RANGE=SLICE_X78Y64:SLICE_X107Y71;
INST "pkt_comm/bcast_net/node[8].r*" AREA_GROUP="node8";
INST "pkt_comm/units[2].unit_io_regs/stage[2].r*" AREA_GROUP="node8";
INST "pkt_comm/units[3].unit_io_regs/stage[2].r*" AREA_GROUP="node8";
INST "pkt_comm/units[8].unit_io_regs/stage[2].r*" AREA_GROUP="node8";
INST "pkt_comm/units[9].unit_io_regs/stage[2].r*" AREA_GROUP="node8";
INST "pkt_comm/units[11].unit_io_regs/stage[2].r*" AREA_GROUP="node8";

AREA_GROUP "node9" RANGE=SLICE_X86Y91:SLICE_X97Y97;
INST "pkt_comm/bcast_net/node[9].r*" AREA_GROUP="node9";
INST "pkt_comm/units[2].unit_io_regs/stage[3].r*" AREA_GROUP="node9";
INST "pkt_comm/units[3].unit_io_regs/stage[3].r*" AREA_GROUP="node9";
INST "pkt_comm/units[9].unit_io_regs/stage[3].r*" AREA_GROUP="node9";
INST "pkt_comm/units[11].unit_io_regs/stage[3].r*" AREA_GROUP="node9";

AREA_GROUP "node10" RANGE=SLICE_X86Y141:SLICE_X87Y143;
INST "pkt_comm/bcast_net/node[10].r*" AREA_GROUP="node10";
INST "pkt_comm/units[2].unit_io_regs/stage[4].r*" AREA_GROUP="node10";
INST "pkt_comm/units[3].unit_io_regs/stage[4].r*" AREA_GROUP="node10";
INST "pkt_comm/units[11].unit_io_regs/stage[4].r*" AREA_GROUP="node10";


// ===========================================================
// Units - left side
// Unit 0
#
AREA_GROUP "u0_0" RANGE=SLICE_X0Y174:SLICE_X21Y191; # 22x16
AREA_GROUP "u0_0" RANGE=RAMB8_X0Y86:RAMB8_X0Y95;
AREA_GROUP "u0_0" RANGE=RAMB16_X0Y86:RAMB16_X0Y94;
INST "pkt_comm/units[0].unit/cores[0].core" AREA_GROUP="u0_0";

AREA_GROUP "u0_1" RANGE=SLICE_X0Y158:SLICE_X21Y173; # 22x16
AREA_GROUP "u0_1" RANGE=RAMB8_X0Y78:RAMB8_X0Y85;
AREA_GROUP "u0_1" RANGE=RAMB16_X0Y78:RAMB16_X0Y84;
INST "pkt_comm/units[0].unit/cores[1].core" AREA_GROUP="u0_1";

AREA_GROUP "u0_2" RANGE=SLICE_X0Y141:SLICE_X19Y157,SLICE_X0Y140:SLICE_X9Y140; # 20x17.5
AREA_GROUP "u0_2" RANGE=RAMB8_X0Y70:RAMB8_X0Y77;
AREA_GROUP "u0_2" RANGE=RAMB16_X0Y70:RAMB16_X0Y76;
INST "pkt_comm/units[0].unit/cores[2].core" AREA_GROUP="u0_2";

AREA_GROUP "u0_3" RANGE=SLICE_X20Y144:SLICE_X41Y157,SLICE_X22Y158:SLICE_X41Y159; # 22x16 X1
AREA_GROUP "u0_3" RANGE=RAMB8_X1Y72:RAMB8_X1Y79;
AREA_GROUP "u0_3" RANGE=RAMB16_X1Y72:RAMB16_X1Y78;
INST "pkt_comm/units[0].unit/cores[3].core" AREA_GROUP="u0_3";

AREA_GROUP "c0" RANGE=SLICE_X22Y160:SLICE_X39Y175,SLICE_X22Y176:SLICE_X33Y191;
AREA_GROUP "c0" RANGE=RAMB8_X1Y80:RAMB8_X1Y95;
AREA_GROUP "c0" RANGE=RAMB16_X1Y80:RAMB16_X1Y94;
INST "pkt_comm/units[0].unit/ctrl" AREA_GROUP="c0";

// Unit 1
AREA_GROUP "u1_0" RANGE=SLICE_X0Y123:SLICE_X19Y139,SLICE_X10Y140:SLICE_X19Y140; # 20x17.5
AREA_GROUP "u1_0" RANGE=RAMB8_X0Y62:RAMB8_X0Y69;
AREA_GROUP "u1_0" RANGE=RAMB16_X0Y62:RAMB16_X0Y68;
INST "pkt_comm/units[1].unit/cores[0].core" AREA_GROUP="u1_0";

AREA_GROUP "u1_1" RANGE=SLICE_X0Y106:SLICE_X19Y122,SLICE_X0Y105:SLICE_X9Y105; # 20x17.5
AREA_GROUP "u1_1" RANGE=RAMB8_X0Y54:RAMB8_X0Y61;
AREA_GROUP "u1_1" RANGE=RAMB16_X0Y54:RAMB16_X0Y60;
INST "pkt_comm/units[1].unit/cores[1].core" AREA_GROUP="u1_1";

AREA_GROUP "u1_2" RANGE=SLICE_X20Y128:SLICE_X41Y143; # 22x16 X1
AREA_GROUP "u1_2" RANGE=RAMB8_X1Y64:RAMB8_X1Y71;
AREA_GROUP "u1_2" RANGE=RAMB16_X1Y64:RAMB16_X1Y70;
INST "pkt_comm/units[1].unit/cores[2].core" AREA_GROUP="u1_2";

AREA_GROUP "u1_3" RANGE=SLICE_X20Y96:SLICE_X41Y111; # 22x16 X1
AREA_GROUP "u1_3" RANGE=RAMB8_X1Y48:RAMB8_X1Y55;
AREA_GROUP "u1_3" RANGE=RAMB16_X1Y48:RAMB16_X1Y54;
INST "pkt_comm/units[1].unit/cores[3].core" AREA_GROUP="u1_3";

AREA_GROUP "c1" RANGE=SLICE_X20Y112:SLICE_X41Y127; # 22x16 X1
AREA_GROUP "c1" RANGE=RAMB8_X1Y56:RAMB8_X1Y63;
AREA_GROUP "c1" RANGE=RAMB16_X1Y56:RAMB16_X1Y62;
INST "pkt_comm/units[1].unit/ctrl" AREA_GROUP="c1";

// Unit 2
AREA_GROUP "u2_0" RANGE=SLICE_X64Y160:SLICE_X85Y175; # 22x16 X3
AREA_GROUP "u2_0" RANGE=RAMB8_X3Y80:RAMB8_X3Y87;
AREA_GROUP "u2_0" RANGE=RAMB16_X3Y80:RAMB16_X3Y86;
INST "pkt_comm/units[2].unit/cores[0].core" AREA_GROUP="u2_0";

AREA_GROUP "u2_1" RANGE=SLICE_X86Y144:SLICE_X107Y157,SLICE_X86Y158:SLICE_X105Y159; # 22x16 X4
AREA_GROUP "u2_1" RANGE=RAMB8_X4Y72:RAMB8_X4Y79;
AREA_GROUP "u2_1" RANGE=RAMB16_X4Y72:RAMB16_X4Y78;
INST "pkt_comm/units[2].unit/cores[1].core" AREA_GROUP="u2_1";

AREA_GROUP "u2_2" RANGE=SLICE_X106Y174:SLICE_X127Y189; # 22x16 X5
AREA_GROUP "u2_2" RANGE=RAMB8_X5Y86:RAMB8_X5Y95;
AREA_GROUP "u2_2" RANGE=RAMB16_X5Y86:RAMB16_X5Y94;
INST "pkt_comm/units[2].unit/cores[2].core" AREA_GROUP="u2_2";

AREA_GROUP "u2_3" RANGE=SLICE_X106Y158:SLICE_X127Y173; # 22x16 X5
AREA_GROUP "u2_3" RANGE=RAMB8_X5Y78:RAMB8_X5Y85;
AREA_GROUP "u2_3" RANGE=RAMB16_X5Y78:RAMB16_X5Y84;
INST "pkt_comm/units[2].unit/cores[3].core" AREA_GROUP="u2_3";

AREA_GROUP "c2" RANGE=SLICE_X86Y160:SLICE_X105Y182;
AREA_GROUP "c2" RANGE=RAMB8_X4Y80:RAMB8_X4Y89;
AREA_GROUP "c2" RANGE=RAMB16_X4Y80:RAMB16_X4Y88;
INST "pkt_comm/units[2].unit/ctrl" AREA_GROUP="c2";

// Unit 3
AREA_GROUP "u3_0" RANGE=SLICE_X88Y128:SLICE_X107Y143,SLICE_X86Y128:SLICE_X87Y140;
AREA_GROUP "u3_0" RANGE=RAMB8_X4Y64:RAMB8_X4Y71;
AREA_GROUP "u3_0" RANGE=RAMB16_X4Y64:RAMB16_X4Y70;
INST "pkt_comm/units[3].unit/cores[0].core" AREA_GROUP="u3_0";

AREA_GROUP "u3_1" RANGE=SLICE_X86Y112:SLICE_X107Y127;
AREA_GROUP "u3_1" RANGE=RAMB8_X4Y56:RAMB8_X4Y63;
AREA_GROUP "u3_1" RANGE=RAMB16_X4Y56:RAMB16_X4Y62;
INST "pkt_comm/units[3].unit/cores[1].core" AREA_GROUP="u3_1";

AREA_GROUP "u3_2" RANGE=SLICE_X108Y141:SLICE_X127Y157,SLICE_X108Y140:SLICE_X115Y140; # 20x17.5
AREA_GROUP "u3_2" RANGE=RAMB8_X5Y70:RAMB8_X5Y77;
AREA_GROUP "u3_2" RANGE=RAMB16_X5Y70:RAMB16_X5Y76;
INST "pkt_comm/units[3].unit/cores[2].core" AREA_GROUP="u3_2";

AREA_GROUP "u3_3" RANGE=SLICE_X108Y106:SLICE_X127Y122,SLICE_X108Y105:SLICE_X117Y105; # 20x17.5
AREA_GROUP "u3_3" RANGE=RAMB8_X5Y54:RAMB8_X5Y61;
AREA_GROUP "u3_3" RANGE=RAMB16_X5Y54:RAMB16_X5Y60;
INST "pkt_comm/units[3].unit/cores[3].core" AREA_GROUP="u3_3";

AREA_GROUP "c3" RANGE=SLICE_X108Y123:SLICE_X127Y139,SLICE_X116Y140:SLICE_X127Y140; # 20x17.5
AREA_GROUP "c3" RANGE=RAMB8_X5Y62:RAMB8_X5Y69;
AREA_GROUP "c3" RANGE=RAMB16_X5Y62:RAMB16_X5Y68;
INST "pkt_comm/units[3].unit/ctrl" AREA_GROUP="c3";

// Unit 4
AREA_GROUP "u4_0" RANGE=SLICE_X0Y18:SLICE_X19Y34,SLICE_X10Y35:SLICE_X19Y35;
AREA_GROUP "u4_0" RANGE=RAMB8_X0Y10:RAMB8_X0Y17;
AREA_GROUP "u4_0" RANGE=RAMB16_X0Y10:RAMB16_X0Y16;
INST "pkt_comm/units[4].unit/cores[0].core" AREA_GROUP="u4_0";

AREA_GROUP "u4_1" RANGE=SLICE_X0Y2:SLICE_X21Y17;
AREA_GROUP "u4_1" RANGE=RAMB8_X0Y0:RAMB8_X0Y9;
AREA_GROUP "u4_1" RANGE=RAMB16_X0Y0:RAMB16_X0Y8;
INST "pkt_comm/units[4].unit/cores[1].core" AREA_GROUP="u4_1";

AREA_GROUP "u4_2" RANGE=SLICE_X42Y32:SLICE_X63Y47; # X2
AREA_GROUP "u4_2" RANGE=RAMB8_X2Y16:RAMB8_X2Y23;
AREA_GROUP "u4_2" RANGE=RAMB16_X2Y16:RAMB16_X2Y22;
INST "pkt_comm/units[4].unit/cores[3].core" AREA_GROUP="u4_3";

AREA_GROUP "u4_3" RANGE=SLICE_X20Y32:SLICE_X41Y47; # X1
AREA_GROUP "u4_3" RANGE=RAMB8_X1Y16:RAMB8_X1Y23;
AREA_GROUP "u4_3" RANGE=RAMB16_X1Y16:RAMB16_X1Y22;
INST "pkt_comm/units[4].unit/cores[2].core" AREA_GROUP="u4_2";

AREA_GROUP "c4" RANGE=SLICE_X20Y18:SLICE_X41Y31,SLICE_X22Y16:SLICE_X41Y17; # 22x16 X1
AREA_GROUP "c4" RANGE=RAMB8_X1Y8:RAMB8_X1Y15;
AREA_GROUP "c4" RANGE=RAMB16_X1Y8:RAMB16_X1Y14;
INST "pkt_comm/units[4].unit/ctrl" AREA_GROUP="c4";

// Unit 5
AREA_GROUP "u5_0" RANGE=SLICE_X0Y53:SLICE_X19Y69,SLICE_X10Y70:SLICE_X19Y70;
AREA_GROUP "u5_0" RANGE=RAMB8_X0Y26:RAMB8_X0Y33;
AREA_GROUP "u5_0" RANGE=RAMB16_X0Y26:RAMB16_X0Y32;
INST "pkt_comm/units[5].unit/cores[0].core" AREA_GROUP="u5_0";

AREA_GROUP "u5_1" RANGE=SLICE_X0Y36:SLICE_X19Y52,SLICE_X0Y35:SLICE_X9Y35;
AREA_GROUP "u5_1" RANGE=RAMB8_X0Y18:RAMB8_X0Y25;
AREA_GROUP "u5_1" RANGE=RAMB16_X0Y18:RAMB16_X0Y24;
INST "pkt_comm/units[5].unit/cores[1].core" AREA_GROUP="u5_1";

AREA_GROUP "u5_2" RANGE=SLICE_X20Y64:SLICE_X41Y79; # 22x16 X1
AREA_GROUP "u5_2" RANGE=RAMB8_X1Y32:RAMB8_X1Y39;
AREA_GROUP "u5_2" RANGE=RAMB16_X1Y32:RAMB16_X1Y40;
INST "pkt_comm/units[5].unit/cores[2].core" AREA_GROUP="u5_2";

AREA_GROUP "u5_3" RANGE=SLICE_X42Y48:SLICE_X63Y63; # 22x16 X2
AREA_GROUP "u5_3" RANGE=RAMB8_X2Y24:RAMB8_X2Y31;
AREA_GROUP "u5_3" RANGE=RAMB16_X2Y24:RAMB16_X2Y30;
INST "pkt_comm/units[5].unit/cores[3].core" AREA_GROUP="u5_3";

AREA_GROUP "c5" RANGE=SLICE_X20Y48:SLICE_X41Y63; # 22x16 X1
AREA_GROUP "c5" RANGE=RAMB8_X1Y24:RAMB8_X1Y31;
AREA_GROUP "c5" RANGE=RAMB16_X1Y24:RAMB16_X1Y30;
INST "pkt_comm/units[5].unit/ctrl" AREA_GROUP="c5";

// Unit 6
AREA_GROUP "u6_0" RANGE=SLICE_X64Y16:SLICE_X85Y31;
AREA_GROUP "u6_0" RANGE=RAMB8_X3Y8:RAMB8_X3Y15;
AREA_GROUP "u6_0" RANGE=RAMB16_X3Y8:RAMB16_X3Y14;
INST "pkt_comm/units[6].unit/cores[0].core" AREA_GROUP="u6_0";

AREA_GROUP "u6_1" RANGE=SLICE_X86Y32:SLICE_X107Y47;
AREA_GROUP "u6_1" RANGE=RAMB8_X4Y16:RAMB8_X4Y23;
AREA_GROUP "u6_1" RANGE=RAMB16_X4Y16:RAMB16_X4Y22;
INST "pkt_comm/units[6].unit/cores[1].core" AREA_GROUP="u6_1";

AREA_GROUP "u6_2" RANGE=SLICE_X108Y18:SLICE_X127Y34,SLICE_X118Y35:SLICE_X127Y35;
AREA_GROUP "u6_2" RANGE=RAMB8_X5Y10:RAMB8_X5Y17;
AREA_GROUP "u6_2" RANGE=RAMB16_X5Y10:RAMB16_X5Y16;
INST "pkt_comm/units[6].unit/cores[2].core" AREA_GROUP="u6_2";

AREA_GROUP "u6_3" RANGE=SLICE_X106Y2:SLICE_X127Y15,SLICE_X108Y16:SLICE_X127Y17;
AREA_GROUP "u6_3" RANGE=RAMB8_X5Y0:RAMB8_X5Y9;
AREA_GROUP "u6_3" RANGE=RAMB16_X5Y0:RAMB16_X5Y8;
INST "pkt_comm/units[6].unit/cores[3].core" AREA_GROUP="u6_3";

AREA_GROUP "c6" RANGE=SLICE_X86Y16:SLICE_X107Y31;
AREA_GROUP "c6" RANGE=RAMB8_X4Y8:RAMB8_X4Y15;
AREA_GROUP "c6" RANGE=RAMB16_X4Y8:RAMB16_X4Y14;
INST "pkt_comm/units[6].unit/ctrl" AREA_GROUP="c6";

// Unit 7
AREA_GROUP "u7_0" RANGE=SLICE_X64Y48:SLICE_X83Y63,SLICE_X84Y48:SLICE_X85Y59;
AREA_GROUP "u7_0" RANGE=RAMB8_X3Y24:RAMB8_X3Y31;
AREA_GROUP "u7_0" RANGE=RAMB16_X3Y24:RAMB16_X3Y30;
INST "pkt_comm/units[7].unit/cores[0].core" AREA_GROUP="u7_0";

AREA_GROUP "u7_1" RANGE=SLICE_X64Y32:SLICE_X83Y47,SLICE_X84Y36:SLICE_X85Y47;
AREA_GROUP "u7_1" RANGE=RAMB8_X3Y16:RAMB8_X3Y23;
AREA_GROUP "u7_1" RANGE=RAMB16_X3Y16:RAMB16_X3Y22;
INST "pkt_comm/units[7].unit/cores[1].core" AREA_GROUP="u7_1";

AREA_GROUP "u7_2" RANGE=SLICE_X108Y53:SLICE_X127Y69,SLICE_X118Y70:SLICE_X127Y70;
AREA_GROUP "u7_2" RANGE=RAMB8_X5Y26:RAMB8_X5Y35;
AREA_GROUP "u7_2" RANGE=RAMB16_X5Y26:RAMB16_X5Y34;
INST "pkt_comm/units[7].unit/cores[2].core" AREA_GROUP="u7_2";

AREA_GROUP "u7_3" RANGE=SLICE_X108Y36:SLICE_X127Y52,SLICE_X108Y35:SLICE_X117Y35;
AREA_GROUP "u7_3" RANGE=RAMB8_X5Y18:RAMB8_X5Y25;
AREA_GROUP "u7_3" RANGE=RAMB16_X5Y18:RAMB16_X5Y24;
INST "pkt_comm/units[7].unit/cores[3].core" AREA_GROUP="u7_3";

AREA_GROUP "c7" RANGE=SLICE_X86Y48:SLICE_X107Y63,SLICE_X84Y60:SLICE_X85Y63;
AREA_GROUP "c7" RANGE=RAMB8_X4Y24:RAMB8_X4Y31;
AREA_GROUP "c7" RANGE=RAMB16_X4Y24:RAMB16_X4Y30;
INST "pkt_comm/units[7].unit/ctrl" AREA_GROUP="c7";

// Unit 8
AREA_GROUP "u8_0" RANGE=SLICE_X64Y64:SLICE_X85Y79;
AREA_GROUP "u8_0" RANGE=RAMB8_X3Y32:RAMB8_X3Y39;
AREA_GROUP "u8_0" RANGE=RAMB16_X3Y32:RAMB16_X3Y38;
INST "pkt_comm/units[8].unit/cores[0].core" AREA_GROUP="u8_0";

AREA_GROUP "u8_1" RANGE=SLICE_X86Y64:SLICE_X107Y79;
AREA_GROUP "u8_1" RANGE=RAMB8_X4Y32:RAMB8_X4Y39;
AREA_GROUP "u8_1" RANGE=RAMB16_X4Y32:RAMB16_X4Y38;
INST "pkt_comm/units[8].unit/cores[1].core" AREA_GROUP="u8_1";

AREA_GROUP "u8_2" RANGE=SLICE_X108Y88:SLICE_X127Y104,SLICE_X118Y105:SLICE_X127Y105;
AREA_GROUP "u8_2" RANGE=RAMB8_X5Y44:RAMB8_X5Y51;
AREA_GROUP "u8_2" RANGE=RAMB16_X5Y44:RAMB16_X5Y50;
INST "pkt_comm/units[8].unit/cores[2].core" AREA_GROUP="u8_2";

AREA_GROUP "u8_3" RANGE=SLICE_X108Y71:SLICE_X127Y87,SLICE_X108Y70:SLICE_X117Y70;
AREA_GROUP "u8_3" RANGE=RAMB8_X5Y36:RAMB8_X5Y43;
AREA_GROUP "u8_3" RANGE=RAMB16_X5Y36:RAMB16_X5Y42;
INST "pkt_comm/units[8].unit/cores[3].core" AREA_GROUP="u8_3";

AREA_GROUP "c8" RANGE=SLICE_X86Y80:SLICE_X107Y95;
AREA_GROUP "c8" RANGE=RAMB8_X4Y40:RAMB8_X4Y47;
AREA_GROUP "c8" RANGE=RAMB16_X4Y40:RAMB16_X4Y46;
INST "pkt_comm/units[8].unit/ctrl" AREA_GROUP="c8";

// Unit 9
AREA_GROUP "u9_0" RANGE=SLICE_X42Y96:SLICE_X63Y111;
AREA_GROUP "u9_0" RANGE=RAMB8_X2Y48:RAMB8_X2Y55;
AREA_GROUP "u9_0" RANGE=RAMB16_X2Y48:RAMB16_X2Y54;
INST "pkt_comm/units[9].unit/cores[0].core" AREA_GROUP="u9_0";

AREA_GROUP "u9_1" RANGE=SLICE_X64Y112:SLICE_X85Y127;
AREA_GROUP "u9_1" RANGE=RAMB8_X3Y56:RAMB8_X3Y63;
AREA_GROUP "u9_1" RANGE=RAMB16_X3Y56:RAMB16_X3Y62;
INST "pkt_comm/units[9].unit/cores[1].core" AREA_GROUP="u9_1";

AREA_GROUP "u9_2" RANGE=SLICE_X64Y80:SLICE_X85Y95;
AREA_GROUP "u9_2" RANGE=RAMB8_X3Y40:RAMB8_X3Y47;
AREA_GROUP "u9_2" RANGE=RAMB16_X3Y40:RAMB16_X3Y46;
INST "pkt_comm/units[9].unit/cores[2].core" AREA_GROUP="u9_2";

AREA_GROUP "u9_3" RANGE=SLICE_X86Y96:SLICE_X107Y111;
AREA_GROUP "u9_3" RANGE=RAMB8_X4Y48:RAMB8_X4Y55;
AREA_GROUP "u9_3" RANGE=RAMB16_X4Y48:RAMB16_X4Y54;
INST "pkt_comm/units[9].unit/cores[3].core" AREA_GROUP="u9_3";

AREA_GROUP "c9" RANGE=SLICE_X64Y96:SLICE_X85Y111;
AREA_GROUP "c9" RANGE=RAMB8_X3Y48:RAMB8_X3Y55;
AREA_GROUP "c9" RANGE=RAMB16_X3Y48:RAMB16_X3Y54;
INST "pkt_comm/units[9].unit/ctrl" AREA_GROUP="c9";

// Unit 10
AREA_GROUP "u10_0" RANGE=SLICE_X0Y88:SLICE_X19Y104,SLICE_X10Y105:SLICE_X19Y105;
AREA_GROUP "u10_0" RANGE=RAMB8_X0Y44:RAMB8_X0Y51;
AREA_GROUP "u10_0" RANGE=RAMB16_X0Y44:RAMB16_X0Y50;
INST "pkt_comm/units[10].unit/cores[0].core" AREA_GROUP="u10_0";

AREA_GROUP "u10_1" RANGE=SLICE_X0Y71:SLICE_X19Y87,SLICE_X0Y70:SLICE_X9Y70;
AREA_GROUP "u10_1" RANGE=RAMB8_X0Y36:RAMB8_X0Y43;
AREA_GROUP "u10_1" RANGE=RAMB16_X0Y36:RAMB16_X0Y42;
INST "pkt_comm/units[10].unit/cores[1].core" AREA_GROUP="u10_1";

AREA_GROUP "u10_2" RANGE=SLICE_X42Y80:SLICE_X63Y95;
AREA_GROUP "u10_2" RANGE=RAMB8_X2Y40:RAMB8_X2Y47;
AREA_GROUP "u10_2" RANGE=RAMB16_X2Y40:RAMB16_X2Y46;
INST "pkt_comm/units[10].unit/cores[2].core" AREA_GROUP="u10_2";

AREA_GROUP "u10_3" RANGE=SLICE_X42Y64:SLICE_X63Y79;
AREA_GROUP "u10_3" RANGE=RAMB8_X2Y32:RAMB8_X2Y39;
AREA_GROUP "u10_3" RANGE=RAMB16_X2Y32:RAMB16_X2Y38;
INST "pkt_comm/units[10].unit/cores[3].core" AREA_GROUP="u10_3";

AREA_GROUP "c10" RANGE=SLICE_X20Y80:SLICE_X41Y95;
AREA_GROUP "c10" RANGE=RAMB8_X1Y40:RAMB8_X1Y47;
AREA_GROUP "c10" RANGE=RAMB16_X1Y40:RAMB16_X1Y46;
INST "pkt_comm/units[10].unit/ctrl" AREA_GROUP="c10";

// Unit 11
AREA_GROUP "u11_0" RANGE=SLICE_X42Y144:SLICE_X63Y159;
AREA_GROUP "u11_0" RANGE=RAMB8_X2Y72:RAMB8_X2Y79;
AREA_GROUP "u11_0" RANGE=RAMB16_X2Y72:RAMB16_X2Y78;
INST "pkt_comm/units[11].unit/cores[0].core" AREA_GROUP="u11_0";

AREA_GROUP "u11_1" RANGE=SLICE_X42Y128:SLICE_X61Y143,SLICE_X62Y128:SLICE_X63Y138;
AREA_GROUP "u11_1" RANGE=RAMB8_X2Y64:RAMB8_X2Y71;
AREA_GROUP "u11_1" RANGE=RAMB16_X2Y64:RAMB16_X2Y70;
INST "pkt_comm/units[11].unit/cores[1].core" AREA_GROUP="u11_1";

AREA_GROUP "u11_2" RANGE=SLICE_X42Y112:SLICE_X63Y127;
AREA_GROUP "u11_2" RANGE=RAMB8_X2Y56:RAMB8_X2Y63;
AREA_GROUP "u11_2" RANGE=RAMB16_X2Y56:RAMB16_X2Y62;
INST "pkt_comm/units[11].unit/cores[2].core" AREA_GROUP="u11_2";

AREA_GROUP "u11_3" RANGE=SLICE_X64Y144:SLICE_X85Y159;
AREA_GROUP "u11_3" RANGE=RAMB8_X3Y72:RAMB8_X3Y79;
AREA_GROUP "u11_3" RANGE=RAMB16_X3Y72:RAMB16_X3Y78;
INST "pkt_comm/units[11].unit/cores[3].core" AREA_GROUP="u11_3";

AREA_GROUP "c11" RANGE=SLICE_X64Y128:SLICE_X85Y143,SLICE_X62Y139:SLICE_X63Y143;
AREA_GROUP "c11" RANGE=RAMB8_X3Y64:RAMB8_X3Y71;
AREA_GROUP "c11" RANGE=RAMB16_X3Y64:RAMB16_X3Y70;
INST "pkt_comm/units[11].unit/ctrl" AREA_GROUP="c11";


// ===========================================================
// pkt_comm
//
AREA_GROUP "pkt_comm" RANGE=SLICE_X52Y0:SLICE_X79Y7,SLICE_X50Y8:SLICE_X81Y15,SLICE_X44Y16:SLICE_X61Y25;
AREA_GROUP "pkt_comm" RANGE=RAMB8_X2Y8:RAMB8_X2Y15;
AREA_GROUP "pkt_comm" RANGE=RAMB16_X2Y8:RAMB16_X2Y14;

INST "pkt_comm/inpkt_header*" AREA_GROUP="pkt_comm";
INST "pkt_comm/word_gen*" AREA_GROUP="pkt_comm";
INST "pkt_comm/cmp_config*" AREA_GROUP="pkt_comm";
INST "pkt_comm/arbiter_tx*" AREA_GROUP="pkt_comm";
INST "pkt_comm/arbiter_rx*" AREA_GROUP="pkt_comm";
INST "pkt_comm/comparator*" AREA_GROUP="pkt_comm";
INST "pkt_comm/outpkt*" AREA_GROUP="pkt_comm";
INST "pkt_comm/rd_en*" AREA_GROUP="pkt_comm";
INST "pkt_comm/word_list*" AREA_GROUP="pkt_comm";
INST "input_fifo/fifo_input1*" AREA_GROUP="pkt_comm";
INST "output_fifo/fifo_output1*" AREA_GROUP="pkt_comm";
INST "hs_io_inst*" AREA_GROUP="pkt_comm";
INST "vcr_inst*" AREA_GROUP="pkt_comm";

AREA_GROUP "area_input0" RANGE=SLICE_X28Y2:SLICE_X33Y15;
AREA_GROUP "area_input0" RANGE=RAMB16_X1Y0:RAMB16_X1Y6;
INST "input_fifo/fifo_input0*" AREA_GROUP="area_input0";

AREA_GROUP "area_output" RANGE=SLICE_X98Y0:SLICE_X103Y15;
AREA_GROUP "area_output" RANGE=RAMB16_X4Y0:RAMB16_X4Y6;
INST "output_fifo/fifo_output0*" AREA_GROUP="area_output";


// ===========================================================
// procb
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_bytes_limit_t*" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_addr_t*" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_total_t*" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_finish_ctx_t" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_padded0x80_t" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_comp_active_t" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/saved_procb_active_t" TIG;
NET "pkt_comm/units[*].unit/ctrl/engine/process_bytes/loaded_bytes_left_t*" TIG;
// cpu
NET "pkt_comm/units[*].unit/ctrl/cpu/uob_thread_num*" TIG;

NET "pkt_comm/mode_cmp" TIG;

