package arm64

import (
	"encoding/hex"
	"testing"

	"github.com/tetratelabs/wazero/internal/asm"
	"github.com/tetratelabs/wazero/internal/testing/require"
)

func TestAssemblerImpl_EncodeTwoRegistersToRegister(t *testing.T) {
	t.Run("error", func(t *testing.T) {
		tests := []struct {
			n      *nodeImpl
			expErr string
		}{
			{
				n: &nodeImpl{
					instruction: ADR, types: operandTypesTwoRegistersToRegister,
					srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
				},
				expErr: "ADR is unsupported for TwoRegistersToRegister type",
			},
		}

		for _, tt := range tests {
			tc := tt
			a := NewAssembler(asm.NilRegister)
			err := a.encodeTwoRegistersToRegister(tc.n)
			require.EqualError(t, err, tc.expErr)
		}
	})

	tests := []struct {
		name           string
		inst           asm.Instruction
		src, src2, dst asm.Register
		exp            []byte
	}{
		{name: "src=RZR,src2=RZR,dst=RZR", inst: AND, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x8a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: AND, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: AND, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: AND, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: AND, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: AND, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: AND, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x8a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: AND, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: AND, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: AND, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x8a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: AND, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x8a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: AND, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x8a}},
		{name: "src=R10,src2=R10,dst=R10", inst: AND, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8a}},
		{name: "src=R10,src2=R10,dst=R30", inst: AND, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x8a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: AND, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x8a}},
		{name: "src=R10,src2=R30,dst=R10", inst: AND, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x8a}},
		{name: "src=R10,src2=R30,dst=R30", inst: AND, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: AND, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: AND, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x8a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: AND, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x8a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: AND, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x8a}},
		{name: "src=R30,src2=R10,dst=R10", inst: AND, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8a}},
		{name: "src=R30,src2=R10,dst=R30", inst: AND, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x8a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: AND, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x8a}},
		{name: "src=R30,src2=R30,dst=R10", inst: AND, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x8a}},
		{name: "src=R30,src2=R30,dst=R30", inst: AND, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xa}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xa}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ANDW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xa}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xa}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xa}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ANDW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xa}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xa}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xa}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ANDW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xa}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xa}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xa}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ANDW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xa}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ANDW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xa}},
		{name: "src=R10,src2=R10,dst=R10", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xa}},
		{name: "src=R10,src2=R10,dst=R30", inst: ANDW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xa}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ANDW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xa}},
		{name: "src=R10,src2=R30,dst=R10", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xa}},
		{name: "src=R10,src2=R30,dst=R30", inst: ANDW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xa}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xa}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xa}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ANDW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xa}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ANDW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xa}},
		{name: "src=R30,src2=R10,dst=R10", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xa}},
		{name: "src=R30,src2=R10,dst=R30", inst: ANDW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xa}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ANDW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xa}},
		{name: "src=R30,src2=R30,dst=R10", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xa}},
		{name: "src=R30,src2=R30,dst=R30", inst: ANDW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xa}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xaa}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xaa}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ORR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ORR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ORR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ORR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xaa}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ORR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xaa}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ORR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xaa}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ORR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ORR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xaa}},
		{name: "src=R10,src2=R10,dst=R10", inst: ORR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xaa}},
		{name: "src=R10,src2=R10,dst=R30", inst: ORR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xaa}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ORR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xaa}},
		{name: "src=R10,src2=R30,dst=R10", inst: ORR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xaa}},
		{name: "src=R10,src2=R30,dst=R30", inst: ORR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xaa}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ORR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xaa}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ORR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ORR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xaa}},
		{name: "src=R30,src2=R10,dst=R10", inst: ORR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xaa}},
		{name: "src=R30,src2=R10,dst=R30", inst: ORR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xaa}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ORR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xaa}},
		{name: "src=R30,src2=R30,dst=R10", inst: ORR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xaa}},
		{name: "src=R30,src2=R30,dst=R30", inst: ORR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xaa}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ORRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ORRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x2a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ORRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x2a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x2a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x2a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ORRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x2a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ORRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x2a}},
		{name: "src=R10,src2=R10,dst=R10", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x2a}},
		{name: "src=R10,src2=R10,dst=R30", inst: ORRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x2a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ORRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x2a}},
		{name: "src=R10,src2=R30,dst=R10", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x2a}},
		{name: "src=R10,src2=R30,dst=R30", inst: ORRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x2a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x2a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x2a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ORRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x2a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ORRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x2a}},
		{name: "src=R30,src2=R10,dst=R10", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x2a}},
		{name: "src=R30,src2=R10,dst=R30", inst: ORRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x2a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ORRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x2a}},
		{name: "src=R30,src2=R30,dst=R10", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x2a}},
		{name: "src=R30,src2=R30,dst=R30", inst: ORRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x2a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xca}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xca}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: EOR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xca}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: EOR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xca}},
		{name: "src=RZR,src2=R10,dst=R10", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xca}},
		{name: "src=RZR,src2=R10,dst=R30", inst: EOR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xca}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: EOR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xca}},
		{name: "src=RZR,src2=R30,dst=R10", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xca}},
		{name: "src=RZR,src2=R30,dst=R30", inst: EOR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xca}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: EOR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xca}},
		{name: "src=R10,src2=RZR,dst=R10", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xca}},
		{name: "src=R10,src2=RZR,dst=R30", inst: EOR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xca}},
		{name: "src=R10,src2=R10,dst=RZR", inst: EOR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xca}},
		{name: "src=R10,src2=R10,dst=R10", inst: EOR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xca}},
		{name: "src=R10,src2=R10,dst=R30", inst: EOR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xca}},
		{name: "src=R10,src2=R30,dst=RZR", inst: EOR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xca}},
		{name: "src=R10,src2=R30,dst=R10", inst: EOR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xca}},
		{name: "src=R10,src2=R30,dst=R30", inst: EOR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xca}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: EOR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xca}},
		{name: "src=R30,src2=RZR,dst=R10", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xca}},
		{name: "src=R30,src2=RZR,dst=R30", inst: EOR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xca}},
		{name: "src=R30,src2=R10,dst=RZR", inst: EOR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xca}},
		{name: "src=R30,src2=R10,dst=R10", inst: EOR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xca}},
		{name: "src=R30,src2=R10,dst=R30", inst: EOR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xca}},
		{name: "src=R30,src2=R30,dst=RZR", inst: EOR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xca}},
		{name: "src=R30,src2=R30,dst=R10", inst: EOR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xca}},
		{name: "src=R30,src2=R30,dst=R30", inst: EOR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xca}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: EORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: EORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: EORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: EORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: EORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: EORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: EORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: EORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4a}},
		{name: "src=R10,src2=R10,dst=R10", inst: EORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4a}},
		{name: "src=R10,src2=R10,dst=R30", inst: EORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: EORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4a}},
		{name: "src=R10,src2=R30,dst=R10", inst: EORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4a}},
		{name: "src=R10,src2=R30,dst=R30", inst: EORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: EORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: EORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: EORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4a}},
		{name: "src=R30,src2=R10,dst=R10", inst: EORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4a}},
		{name: "src=R30,src2=R10,dst=R30", inst: EORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: EORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4a}},
		{name: "src=R30,src2=R30,dst=R10", inst: EORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4a}},
		{name: "src=R30,src2=R30,dst=R30", inst: EORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ASR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ASR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ASR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ASR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ASR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ASR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ASR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ASR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: ASR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: ASR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ASR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: ASR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: ASR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ASR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ASR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ASR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: ASR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: ASR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ASR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: ASR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: ASR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ASRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ASRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ASRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ASRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ASRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: ASRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ASRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: ASRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2b, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2b, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ASRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2b, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ASRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x29, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x29, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: ASRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x29, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ASRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2b, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2b, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: ASRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2b, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: LSL, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: LSL, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: LSL, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: LSL, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: LSL, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: LSL, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: LSL, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: LSL, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: LSL, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: LSL, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: LSL, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: LSL, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: LSL, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: LSL, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: LSL, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: LSL, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: LSL, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: LSL, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: LSL, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: LSL, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: LSL, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: LSLW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: LSLW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: LSLW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: LSLW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: LSLW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: LSLW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: LSLW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: LSLW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x23, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x23, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: LSLW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x23, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: LSLW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x21, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x21, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: LSLW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x21, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: LSLW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x23, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x23, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: LSLW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x23, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: LSR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: LSR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: LSR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: LSR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: LSR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: LSR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: LSR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: LSR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: LSR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: LSR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: LSR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: LSR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: LSR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: LSR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: LSR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: LSR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: LSR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: LSR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: LSR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: LSR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: LSR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: LSRW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: LSRW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: LSRW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: LSRW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: LSRW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: LSRW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: LSRW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: LSRW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x27, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x27, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: LSRW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x27, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: LSRW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x25, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x25, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: LSRW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x25, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: LSRW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x27, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x27, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: LSRW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x27, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: ROR, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: ROR, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: ROR, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: ROR, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: ROR, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: ROR, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: ROR, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: ROR, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: ROR, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: ROR, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: ROR, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: ROR, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: ROR, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: ROR, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: ROR, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: ROR, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: ROR, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: ROR, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: ROR, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: ROR, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: ROR, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: RORW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: RORW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: RORW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: RORW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: RORW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: RORW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: RORW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: RORW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: RORW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: RORW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: RORW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: RORW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: RORW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: RORW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x2f, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x2f, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: RORW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x2f, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: RORW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x2d, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: RORW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x2d, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: RORW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x2d, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: RORW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x2f, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: RORW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x2f, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: RORW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x2f, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: SDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: SDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: SDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: SDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: SDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: SDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: SDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: SDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: SDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: SDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: SDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: SDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: SDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: SDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: SDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: SDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: SDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: SDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xf, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: SDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xf, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0xd, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: SDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0xd, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xf, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xf, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: SDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: UDIV, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: UDIV, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x9a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: UDIV, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x9a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: UDIV, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: UDIV, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R10", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}},
		{name: "src=R10,src2=R10,dst=R30", inst: UDIV, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: UDIV, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R10", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x9a}},
		{name: "src=R10,src2=R30,dst=R30", inst: UDIV, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x9a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: UDIV, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: UDIV, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R10", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}},
		{name: "src=R30,src2=R10,dst=R30", inst: UDIV, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: UDIV, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R10", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x9a}},
		{name: "src=R30,src2=R30,dst=R30", inst: UDIV, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xdf, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: UDIVW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R10,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R10", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xdf, 0x1a}},
		{name: "src=RZR,src2=R30,dst=R30", inst: UDIVW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R10", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xca, 0x1a}},
		{name: "src=R10,src2=RZR,dst=R30", inst: UDIVW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R10", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}},
		{name: "src=R10,src2=R10,dst=R30", inst: UDIVW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=RZR", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R10", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xca, 0x1a}},
		{name: "src=R10,src2=R30,dst=R30", inst: UDIVW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R10", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0xb, 0xde, 0x1a}},
		{name: "src=R30,src2=RZR,dst=R30", inst: UDIVW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0xb, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x9, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R10", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}},
		{name: "src=R30,src2=R10,dst=R30", inst: UDIVW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x9, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=RZR", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0xb, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R10", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0xb, 0xde, 0x1a}},
		{name: "src=R30,src2=R30,dst=R30", inst: UDIVW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: SUB, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: SUB, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R10,dst=R10", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R10,dst=R30", inst: SUB, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: SUB, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R30,dst=R10", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0xcb}},
		{name: "src=RZR,src2=R30,dst=R30", inst: SUB, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: SUB, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
		{name: "src=R10,src2=RZR,dst=R10", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}},
		{name: "src=R10,src2=RZR,dst=R30", inst: SUB, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}},
		{name: "src=R10,src2=R10,dst=RZR", inst: SUB, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0xcb}},
		{name: "src=R10,src2=R10,dst=R10", inst: SUB, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}},
		{name: "src=R10,src2=R10,dst=R30", inst: SUB, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0xcb}},
		{name: "src=R10,src2=R30,dst=RZR", inst: SUB, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0xcb}},
		{name: "src=R10,src2=R30,dst=R10", inst: SUB, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0xcb}},
		{name: "src=R10,src2=R30,dst=R30", inst: SUB, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: SUB, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
		{name: "src=R30,src2=RZR,dst=R10", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}},
		{name: "src=R30,src2=RZR,dst=R30", inst: SUB, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}},
		{name: "src=R30,src2=R10,dst=RZR", inst: SUB, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0xcb}},
		{name: "src=R30,src2=R10,dst=R10", inst: SUB, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}},
		{name: "src=R30,src2=R10,dst=R30", inst: SUB, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0xcb}},
		{name: "src=R30,src2=R30,dst=RZR", inst: SUB, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0xcb}},
		{name: "src=R30,src2=R30,dst=R10", inst: SUB, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0xcb}},
		{name: "src=R30,src2=R30,dst=R30", inst: SUB, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}},
		{name: "src=RZR,src2=RZR,dst=RZR", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}},
		{name: "src=RZR,src2=RZR,dst=R10", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}},
		{name: "src=RZR,src2=RZR,dst=R30", inst: SUBW, src: RegRZR, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R10,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R10,dst=R10", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R10,dst=R30", inst: SUBW, src: RegRZR, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R30,dst=RZR", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R30,dst=R10", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1f, 0x4b}},
		{name: "src=RZR,src2=R30,dst=R30", inst: SUBW, src: RegRZR, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x4b}},
		{name: "src=R10,src2=RZR,dst=RZR", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}},
		{name: "src=R10,src2=RZR,dst=R10", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}},
		{name: "src=R10,src2=RZR,dst=R30", inst: SUBW, src: RegR10, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}},
		{name: "src=R10,src2=R10,dst=RZR", inst: SUBW, src: RegR10, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xa, 0x4b}},
		{name: "src=R10,src2=R10,dst=R10", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x4b}},
		{name: "src=R10,src2=R10,dst=R30", inst: SUBW, src: RegR10, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xa, 0x4b}},
		{name: "src=R10,src2=R30,dst=RZR", inst: SUBW, src: RegR10, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xa, 0x4b}},
		{name: "src=R10,src2=R30,dst=R10", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xa, 0x4b}},
		{name: "src=R10,src2=R30,dst=R30", inst: SUBW, src: RegR10, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x4b}},
		{name: "src=R30,src2=RZR,dst=RZR", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}},
		{name: "src=R30,src2=RZR,dst=R10", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}},
		{name: "src=R30,src2=RZR,dst=R30", inst: SUBW, src: RegR30, src2: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}},
		{name: "src=R30,src2=R10,dst=RZR", inst: SUBW, src: RegR30, src2: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0x1e, 0x4b}},
		{name: "src=R30,src2=R10,dst=R10", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x4b}},
		{name: "src=R30,src2=R10,dst=R30", inst: SUBW, src: RegR30, src2: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0x1e, 0x4b}},
		{name: "src=R30,src2=R30,dst=RZR", inst: SUBW, src: RegR30, src2: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0x1e, 0x4b}},
		{name: "src=R30,src2=R30,dst=R10", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0x1e, 0x4b}},
		{name: "src=R30,src2=R30,dst=R30", inst: SUBW, src: RegR30, src2: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x4b}},
		{name: "src=V0,src2=V0,dst=V0", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x60, 0x1e}},
		{name: "src=V0,src2=V0,dst=V31", inst: FSUBD, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x60, 0x1e}},
		{name: "src=V0,src2=V31,dst=V0", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x60, 0x1e}},
		{name: "src=V0,src2=V31,dst=V31", inst: FSUBD, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x60, 0x1e}},
		{name: "src=V31,src2=V0,dst=V0", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x7f, 0x1e}},
		{name: "src=V31,src2=V0,dst=V31", inst: FSUBD, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x7f, 0x1e}},
		{name: "src=V31,src2=V31,dst=V0", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x7f, 0x1e}},
		{name: "src=V31,src2=V31,dst=V31", inst: FSUBD, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x7f, 0x1e}},
		{name: "src=V0,src2=V0,dst=V0", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x20, 0x1e}},
		{name: "src=V0,src2=V0,dst=V31", inst: FSUBS, src: RegV0, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x20, 0x1e}},
		{name: "src=V0,src2=V31,dst=V0", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x20, 0x1e}},
		{name: "src=V0,src2=V31,dst=V31", inst: FSUBS, src: RegV0, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x20, 0x1e}},
		{name: "src=V31,src2=V0,dst=V0", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV0, exp: []byte{0x0, 0x38, 0x3f, 0x1e}},
		{name: "src=V31,src2=V0,dst=V31", inst: FSUBS, src: RegV31, src2: RegV0, dst: RegV31, exp: []byte{0x1f, 0x38, 0x3f, 0x1e}},
		{name: "src=V31,src2=V31,dst=V0", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV0, exp: []byte{0xe0, 0x3b, 0x3f, 0x1e}},
		{name: "src=V31,src2=V31,dst=V31", inst: FSUBS, src: RegV31, src2: RegV31, dst: RegV31, exp: []byte{0xff, 0x3b, 0x3f, 0x1e}},
	}

	for _, tc := range tests {
		t.Run(tc.name, func(t *testing.T) {
			a := NewAssembler(asm.NilRegister)
			err := a.encodeTwoRegistersToRegister(&nodeImpl{instruction: tc.inst, srcReg: tc.src, srcReg2: tc.src2, dstReg: tc.dst})
			require.NoError(t, err)

			actual := a.buf.Bytes()
			require.Equal(t, tc.exp, actual[:4])
		})
	}
}

func TestAssemblerImpl_EncodeRegisterAndConstToNone(t *testing.T) {
	t.Run("error", func(t *testing.T) {
		tests := []struct {
			n      *nodeImpl
			expErr string
		}{
			{
				n: &nodeImpl{
					instruction: ADR, types: operandTypesRegisterAndConstToNone,
					srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
				},
				expErr: "ADR is unsupported for RegisterAndConstToNone type",
			},
			{
				n: &nodeImpl{
					instruction: CMP, types: operandTypesRegisterAndConstToNone,
					srcReg: RegR0, srcConst: 12345,
				},
				expErr: "immediate for CMP must fit in 0 to 4095 but got 12345",
			},
			{
				n: &nodeImpl{
					instruction: CMP, types: operandTypesRegisterAndConstToNone,
					srcReg: RegRZR, srcConst: 123,
				},
				expErr: "zero register is not supported for CMP (immediate)",
			},
		}

		for _, tt := range tests {
			tc := tt
			a := NewAssembler(asm.NilRegister)
			err := a.encodeRegisterAndConstToNone(tc.n)
			require.EqualError(t, err, tc.expErr)
		}
	})

	tests := []struct {
		name string
		inst asm.Instruction
		reg  asm.Register
		c    int64
		exp  []byte
	}{
		{name: "R1, 0", inst: CMP, reg: RegR1, c: 0, exp: []byte{0x3f, 0x0, 0x0, 0xf1}},
		{name: "R1, 10", inst: CMP, reg: RegR1, c: 10, exp: []byte{0x3f, 0x28, 0x0, 0xf1}},
		{name: "R1, 100", inst: CMP, reg: RegR1, c: 100, exp: []byte{0x3f, 0x90, 0x1, 0xf1}},
		{name: "R1, 300", inst: CMP, reg: RegR1, c: 300, exp: []byte{0x3f, 0xb0, 0x4, 0xf1}},
		{name: "R1, 4095", inst: CMP, reg: RegR1, c: 4095, exp: []byte{0x3f, 0xfc, 0x3f, 0xf1}},
		{name: "R10, 0", inst: CMP, reg: RegR10, c: 0, exp: []byte{0x5f, 0x1, 0x0, 0xf1}},
		{name: "R10, 10", inst: CMP, reg: RegR10, c: 10, exp: []byte{0x5f, 0x29, 0x0, 0xf1}},
		{name: "R10, 100", inst: CMP, reg: RegR10, c: 100, exp: []byte{0x5f, 0x91, 0x1, 0xf1}},
		{name: "R10, 300", inst: CMP, reg: RegR10, c: 300, exp: []byte{0x5f, 0xb1, 0x4, 0xf1}},
		{name: "R10, 4095", inst: CMP, reg: RegR10, c: 4095, exp: []byte{0x5f, 0xfd, 0x3f, 0xf1}},
		{name: "R30, 0", inst: CMP, reg: RegR30, c: 0, exp: []byte{0xdf, 0x3, 0x0, 0xf1}},
		{name: "R30, 10", inst: CMP, reg: RegR30, c: 10, exp: []byte{0xdf, 0x2b, 0x0, 0xf1}},
		{name: "R30, 100", inst: CMP, reg: RegR30, c: 100, exp: []byte{0xdf, 0x93, 0x1, 0xf1}},
		{name: "R30, 300", inst: CMP, reg: RegR30, c: 300, exp: []byte{0xdf, 0xb3, 0x4, 0xf1}},
		{name: "R30, 4095", inst: CMP, reg: RegR30, c: 4095, exp: []byte{0xdf, 0xff, 0x3f, 0xf1}},
	}

	for _, tc := range tests {
		t.Run(tc.name, func(t *testing.T) {
			a := NewAssembler(asm.NilRegister)
			err := a.encodeRegisterAndConstToNone(&nodeImpl{instruction: tc.inst, srcReg: tc.reg, srcConst: tc.c})
			require.NoError(t, err)

			actual := a.buf.Bytes()
			require.Equal(t, tc.exp, actual[:4])
		})
	}
}

func TestAssemblerImpl_EncodeRegisterToRegister(t *testing.T) {
	t.Run("error", func(t *testing.T) {
		tests := []struct {
			n      *nodeImpl
			expErr string
		}{
			{
				n: &nodeImpl{
					instruction: ADR, types: operandTypesRegisterToRegister,
					srcReg: RegR0, srcReg2: RegR0, dstReg: RegR0,
				},
				expErr: "ADR is unsupported for RegisterToRegister type",
			},
		}

		for _, tt := range tests {
			tc := tt
			a := NewAssembler(asm.NilRegister)
			err := a.encodeRegisterToRegister(tc.n)
			require.EqualError(t, err, tc.expErr)
		}
	})

	tests := []struct {
		name     string
		inst     asm.Instruction
		src, dst asm.Register
		exp      []byte
	}{
		{name: "MOV/src=RegSP,dst=R10", inst: MOVD, src: RegSP, dst: RegR10, exp: []byte{0xea, 0x3, 0x0, 0x91}},
		{name: "MOV/src=RegSP,dst=R30", inst: MOVD, src: RegSP, dst: RegR30, exp: []byte{0xfe, 0x3, 0x0, 0x91}},
		{name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegR10, dst: RegSP, exp: []byte{0x5f, 0x1, 0x0, 0x91}},
		{name: "MOV/src=R10,dst=R10", inst: MOVD, src: RegR30, dst: RegSP, exp: []byte{0xdf, 0x3, 0x0, 0x91}},
		{name: "MOV/src=R10,dst=RegSP", inst: MOVD, src: RegSP, dst: RegSP, exp: []byte{0xff, 0x3, 0x0, 0x91}},
		{name: "ADD/src=RZR,dst=RZR", inst: ADD, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x8b}},
		{name: "ADD/src=RZR,dst=R10", inst: ADD, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0x8b}},
		{name: "ADD/src=RZR,dst=R30", inst: ADD, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0x8b}},
		{name: "ADD/src=R10,dst=RZR", inst: ADD, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x8b}},
		{name: "ADD/src=R10,dst=R10", inst: ADD, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0x8b}},
		{name: "ADD/src=R10,dst=R30", inst: ADD, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0x8b}},
		{name: "ADD/src=R30,dst=RZR", inst: ADD, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x8b}},
		{name: "ADD/src=R30,dst=R10", inst: ADD, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0x8b}},
		{name: "ADD/src=R30,dst=R30", inst: ADD, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0x8b}},
		{name: "ADDW/src=RZR,dst=RZR", inst: ADDW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xb}},
		{name: "ADDW/src=RZR,dst=R10", inst: ADDW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xb}},
		{name: "ADDW/src=RZR,dst=R30", inst: ADDW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xb}},
		{name: "ADDW/src=R10,dst=RZR", inst: ADDW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xb}},
		{name: "ADDW/src=R10,dst=R10", inst: ADDW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xb}},
		{name: "ADDW/src=R10,dst=R30", inst: ADDW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xb}},
		{name: "ADDW/src=R30,dst=RZR", inst: ADDW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xb}},
		{name: "ADDW/src=R30,dst=R10", inst: ADDW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xb}},
		{name: "ADDW/src=R30,dst=R30", inst: ADDW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xb}},
		{name: "SUB/src=RZR,dst=RZR", inst: SUB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
		{name: "SUB/src=RZR,dst=R10", inst: SUB, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1f, 0xcb}},
		{name: "SUB/src=RZR,dst=R30", inst: SUB, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x3, 0x1f, 0xcb}},
		{name: "SUB/src=R10,dst=RZR", inst: SUB, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
		{name: "SUB/src=R10,dst=R10", inst: SUB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xa, 0xcb}},
		{name: "SUB/src=R10,dst=R30", inst: SUB, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x3, 0xa, 0xcb}},
		{name: "SUB/src=R30,dst=RZR", inst: SUB, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
		{name: "SUB/src=R30,dst=R10", inst: SUB, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x1, 0x1e, 0xcb}},
		{name: "SUB/src=R30,dst=R30", inst: SUB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0x1e, 0xcb}},
		{name: "CLZ/src=RZR,dst=RZR", inst: CLZ, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0xda}},
		{name: "CLZ/src=RZR,dst=R10", inst: CLZ, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0xda}},
		{name: "CLZ/src=RZR,dst=R30", inst: CLZ, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0xda}},
		{name: "CLZ/src=R10,dst=RZR", inst: CLZ, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0xda}},
		{name: "CLZ/src=R10,dst=R10", inst: CLZ, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0xda}},
		{name: "CLZ/src=R10,dst=R30", inst: CLZ, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0xda}},
		{name: "CLZ/src=R30,dst=RZR", inst: CLZ, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0xda}},
		{name: "CLZ/src=R30,dst=R10", inst: CLZ, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0xda}},
		{name: "CLZ/src=R30,dst=R30", inst: CLZ, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0xda}},
		{name: "CLZW/src=RZR,dst=RZR", inst: CLZW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x13, 0xc0, 0x5a}},
		{name: "CLZW/src=RZR,dst=R10", inst: CLZW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x13, 0xc0, 0x5a}},
		{name: "CLZW/src=RZR,dst=R30", inst: CLZW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x13, 0xc0, 0x5a}},
		{name: "CLZW/src=R10,dst=RZR", inst: CLZW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x11, 0xc0, 0x5a}},
		{name: "CLZW/src=R10,dst=R10", inst: CLZW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x11, 0xc0, 0x5a}},
		{name: "CLZW/src=R10,dst=R30", inst: CLZW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x11, 0xc0, 0x5a}},
		{name: "CLZW/src=R30,dst=RZR", inst: CLZW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x13, 0xc0, 0x5a}},
		{name: "CLZW/src=R30,dst=R10", inst: CLZW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x13, 0xc0, 0x5a}},
		{name: "CLZW/src=R30,dst=R30", inst: CLZW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x13, 0xc0, 0x5a}},
		{name: "CSET/src=COND_EQ,dst=RZR", inst: CSET, src: RegCondEQ, dst: RegRZR, exp: []byte{0xff, 0x17, 0x9f, 0x9a}},
		{name: "CSET/src=COND_EQ,dst=R10", inst: CSET, src: RegCondEQ, dst: RegR10, exp: []byte{0xea, 0x17, 0x9f, 0x9a}},
		{name: "CSET/src=COND_EQ,dst=R30", inst: CSET, src: RegCondEQ, dst: RegR30, exp: []byte{0xfe, 0x17, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NE,dst=RZR", inst: CSET, src: RegCondNE, dst: RegRZR, exp: []byte{0xff, 0x7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NE,dst=R10", inst: CSET, src: RegCondNE, dst: RegR10, exp: []byte{0xea, 0x7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NE,dst=R30", inst: CSET, src: RegCondNE, dst: RegR30, exp: []byte{0xfe, 0x7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HS,dst=RZR", inst: CSET, src: RegCondHS, dst: RegRZR, exp: []byte{0xff, 0x37, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HS,dst=R10", inst: CSET, src: RegCondHS, dst: RegR10, exp: []byte{0xea, 0x37, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HS,dst=R30", inst: CSET, src: RegCondHS, dst: RegR30, exp: []byte{0xfe, 0x37, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LO,dst=RZR", inst: CSET, src: RegCondLO, dst: RegRZR, exp: []byte{0xff, 0x27, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LO,dst=R10", inst: CSET, src: RegCondLO, dst: RegR10, exp: []byte{0xea, 0x27, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LO,dst=R30", inst: CSET, src: RegCondLO, dst: RegR30, exp: []byte{0xfe, 0x27, 0x9f, 0x9a}},
		{name: "CSET/src=COND_MI,dst=RZR", inst: CSET, src: RegCondMI, dst: RegRZR, exp: []byte{0xff, 0x57, 0x9f, 0x9a}},
		{name: "CSET/src=COND_MI,dst=R10", inst: CSET, src: RegCondMI, dst: RegR10, exp: []byte{0xea, 0x57, 0x9f, 0x9a}},
		{name: "CSET/src=COND_MI,dst=R30", inst: CSET, src: RegCondMI, dst: RegR30, exp: []byte{0xfe, 0x57, 0x9f, 0x9a}},
		{name: "CSET/src=COND_PL,dst=RZR", inst: CSET, src: RegCondPL, dst: RegRZR, exp: []byte{0xff, 0x47, 0x9f, 0x9a}},
		{name: "CSET/src=COND_PL,dst=R10", inst: CSET, src: RegCondPL, dst: RegR10, exp: []byte{0xea, 0x47, 0x9f, 0x9a}},
		{name: "CSET/src=COND_PL,dst=R30", inst: CSET, src: RegCondPL, dst: RegR30, exp: []byte{0xfe, 0x47, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VS,dst=RZR", inst: CSET, src: RegCondVS, dst: RegRZR, exp: []byte{0xff, 0x77, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VS,dst=R10", inst: CSET, src: RegCondVS, dst: RegR10, exp: []byte{0xea, 0x77, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VS,dst=R30", inst: CSET, src: RegCondVS, dst: RegR30, exp: []byte{0xfe, 0x77, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VC,dst=RZR", inst: CSET, src: RegCondVC, dst: RegRZR, exp: []byte{0xff, 0x67, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VC,dst=R10", inst: CSET, src: RegCondVC, dst: RegR10, exp: []byte{0xea, 0x67, 0x9f, 0x9a}},
		{name: "CSET/src=COND_VC,dst=R30", inst: CSET, src: RegCondVC, dst: RegR30, exp: []byte{0xfe, 0x67, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HI,dst=RZR", inst: CSET, src: RegCondHI, dst: RegRZR, exp: []byte{0xff, 0x97, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HI,dst=R10", inst: CSET, src: RegCondHI, dst: RegR10, exp: []byte{0xea, 0x97, 0x9f, 0x9a}},
		{name: "CSET/src=COND_HI,dst=R30", inst: CSET, src: RegCondHI, dst: RegR30, exp: []byte{0xfe, 0x97, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LS,dst=RZR", inst: CSET, src: RegCondLS, dst: RegRZR, exp: []byte{0xff, 0x87, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LS,dst=R10", inst: CSET, src: RegCondLS, dst: RegR10, exp: []byte{0xea, 0x87, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LS,dst=R30", inst: CSET, src: RegCondLS, dst: RegR30, exp: []byte{0xfe, 0x87, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GE,dst=RZR", inst: CSET, src: RegCondGE, dst: RegRZR, exp: []byte{0xff, 0xb7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GE,dst=R10", inst: CSET, src: RegCondGE, dst: RegR10, exp: []byte{0xea, 0xb7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GE,dst=R30", inst: CSET, src: RegCondGE, dst: RegR30, exp: []byte{0xfe, 0xb7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LT,dst=RZR", inst: CSET, src: RegCondLT, dst: RegRZR, exp: []byte{0xff, 0xa7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LT,dst=R10", inst: CSET, src: RegCondLT, dst: RegR10, exp: []byte{0xea, 0xa7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LT,dst=R30", inst: CSET, src: RegCondLT, dst: RegR30, exp: []byte{0xfe, 0xa7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GT,dst=RZR", inst: CSET, src: RegCondGT, dst: RegRZR, exp: []byte{0xff, 0xd7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GT,dst=R10", inst: CSET, src: RegCondGT, dst: RegR10, exp: []byte{0xea, 0xd7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_GT,dst=R30", inst: CSET, src: RegCondGT, dst: RegR30, exp: []byte{0xfe, 0xd7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LE,dst=RZR", inst: CSET, src: RegCondLE, dst: RegRZR, exp: []byte{0xff, 0xc7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LE,dst=R10", inst: CSET, src: RegCondLE, dst: RegR10, exp: []byte{0xea, 0xc7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_LE,dst=R30", inst: CSET, src: RegCondLE, dst: RegR30, exp: []byte{0xfe, 0xc7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_AL,dst=RZR", inst: CSET, src: RegCondAL, dst: RegRZR, exp: []byte{0xff, 0xf7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_AL,dst=R10", inst: CSET, src: RegCondAL, dst: RegR10, exp: []byte{0xea, 0xf7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_AL,dst=R30", inst: CSET, src: RegCondAL, dst: RegR30, exp: []byte{0xfe, 0xf7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NV,dst=RZR", inst: CSET, src: RegCondNV, dst: RegRZR, exp: []byte{0xff, 0xe7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NV,dst=R10", inst: CSET, src: RegCondNV, dst: RegR10, exp: []byte{0xea, 0xe7, 0x9f, 0x9a}},
		{name: "CSET/src=COND_NV,dst=R30", inst: CSET, src: RegCondNV, dst: RegR30, exp: []byte{0xfe, 0xe7, 0x9f, 0x9a}},
		{name: "FABSS/src=V0,dst=V0", inst: FABSS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x20, 0x1e}},
		{name: "FABSS/src=V0,dst=V31", inst: FABSS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x20, 0x1e}},
		{name: "FABSS/src=V31,dst=V0", inst: FABSS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x20, 0x1e}},
		{name: "FABSS/src=V31,dst=V31", inst: FABSS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x20, 0x1e}},
		{name: "FABSD/src=V0,dst=V0", inst: FABSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x60, 0x1e}},
		{name: "FABSD/src=V0,dst=V31", inst: FABSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x60, 0x1e}},
		{name: "FABSD/src=V31,dst=V0", inst: FABSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x60, 0x1e}},
		{name: "FABSD/src=V31,dst=V31", inst: FABSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x60, 0x1e}},
		{name: "FNEGS/src=V0,dst=V0", inst: FNEGS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x21, 0x1e}},
		{name: "FNEGS/src=V0,dst=V31", inst: FNEGS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x21, 0x1e}},
		{name: "FNEGS/src=V31,dst=V0", inst: FNEGS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x21, 0x1e}},
		{name: "FNEGS/src=V31,dst=V31", inst: FNEGS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x21, 0x1e}},
		{name: "FNEGD/src=V0,dst=V0", inst: FNEGD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x61, 0x1e}},
		{name: "FNEGD/src=V0,dst=V31", inst: FNEGD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x61, 0x1e}},
		{name: "FNEGD/src=V31,dst=V0", inst: FNEGD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x61, 0x1e}},
		{name: "FNEGD/src=V31,dst=V31", inst: FNEGD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x61, 0x1e}},
		{name: "FSQRTD/src=V0,dst=V0", inst: FSQRTD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x61, 0x1e}},
		{name: "FSQRTD/src=V0,dst=V31", inst: FSQRTD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x61, 0x1e}},
		{name: "FSQRTD/src=V31,dst=V0", inst: FSQRTD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x61, 0x1e}},
		{name: "FSQRTD/src=V31,dst=V31", inst: FSQRTD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x61, 0x1e}},
		{name: "FSQRTS/src=V0,dst=V0", inst: FSQRTS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x21, 0x1e}},
		{name: "FSQRTS/src=V0,dst=V31", inst: FSQRTS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x21, 0x1e}},
		{name: "FSQRTS/src=V31,dst=V0", inst: FSQRTS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x21, 0x1e}},
		{name: "FSQRTS/src=V31,dst=V31", inst: FSQRTS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x21, 0x1e}},
		{name: "FCVTDS/src=V0,dst=V0", inst: FCVTDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x62, 0x1e}},
		{name: "FCVTDS/src=V0,dst=V31", inst: FCVTDS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x62, 0x1e}},
		{name: "FCVTDS/src=V31,dst=V0", inst: FCVTDS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x62, 0x1e}},
		{name: "FCVTDS/src=V31,dst=V31", inst: FCVTDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x62, 0x1e}},
		{name: "FCVTSD/src=V0,dst=V0", inst: FCVTSD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x22, 0x1e}},
		{name: "FCVTSD/src=V0,dst=V31", inst: FCVTSD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x22, 0x1e}},
		{name: "FCVTSD/src=V31,dst=V0", inst: FCVTSD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x22, 0x1e}},
		{name: "FCVTSD/src=V31,dst=V31", inst: FCVTSD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x22, 0x1e}},
		{name: "FRINTMD/src=V0,dst=V0", inst: FRINTMD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x65, 0x1e}},
		{name: "FRINTMD/src=V0,dst=V31", inst: FRINTMD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x65, 0x1e}},
		{name: "FRINTMD/src=V31,dst=V0", inst: FRINTMD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x65, 0x1e}},
		{name: "FRINTMD/src=V31,dst=V31", inst: FRINTMD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x65, 0x1e}},
		{name: "FRINTMS/src=V0,dst=V0", inst: FRINTMS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x25, 0x1e}},
		{name: "FRINTMS/src=V0,dst=V31", inst: FRINTMS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x25, 0x1e}},
		{name: "FRINTMS/src=V31,dst=V0", inst: FRINTMS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x25, 0x1e}},
		{name: "FRINTMS/src=V31,dst=V31", inst: FRINTMS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x25, 0x1e}},
		{name: "FRINTND/src=V0,dst=V0", inst: FRINTND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x64, 0x1e}},
		{name: "FRINTND/src=V0,dst=V31", inst: FRINTND, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x64, 0x1e}},
		{name: "FRINTND/src=V31,dst=V0", inst: FRINTND, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x64, 0x1e}},
		{name: "FRINTND/src=V31,dst=V31", inst: FRINTND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x64, 0x1e}},
		{name: "FRINTNS/src=V0,dst=V0", inst: FRINTNS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x24, 0x1e}},
		{name: "FRINTNS/src=V0,dst=V31", inst: FRINTNS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x24, 0x1e}},
		{name: "FRINTNS/src=V31,dst=V0", inst: FRINTNS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x24, 0x1e}},
		{name: "FRINTNS/src=V31,dst=V31", inst: FRINTNS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x24, 0x1e}},
		{name: "FRINTPD/src=V0,dst=V0", inst: FRINTPD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x64, 0x1e}},
		{name: "FRINTPD/src=V0,dst=V31", inst: FRINTPD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x64, 0x1e}},
		{name: "FRINTPD/src=V31,dst=V0", inst: FRINTPD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x64, 0x1e}},
		{name: "FRINTPD/src=V31,dst=V31", inst: FRINTPD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x64, 0x1e}},
		{name: "FRINTPS/src=V0,dst=V0", inst: FRINTPS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x24, 0x1e}},
		{name: "FRINTPS/src=V0,dst=V31", inst: FRINTPS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x24, 0x1e}},
		{name: "FRINTPS/src=V31,dst=V0", inst: FRINTPS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x24, 0x1e}},
		{name: "FRINTPS/src=V31,dst=V31", inst: FRINTPS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x24, 0x1e}},
		{name: "FRINTZD/src=V0,dst=V0", inst: FRINTZD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x65, 0x1e}},
		{name: "FRINTZD/src=V0,dst=V31", inst: FRINTZD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x65, 0x1e}},
		{name: "FRINTZD/src=V31,dst=V0", inst: FRINTZD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x65, 0x1e}},
		{name: "FRINTZD/src=V31,dst=V31", inst: FRINTZD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x65, 0x1e}},
		{name: "FRINTZS/src=V0,dst=V0", inst: FRINTZS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0xc0, 0x25, 0x1e}},
		{name: "FRINTZS/src=V0,dst=V31", inst: FRINTZS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0xc0, 0x25, 0x1e}},
		{name: "FRINTZS/src=V31,dst=V0", inst: FRINTZS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0xc3, 0x25, 0x1e}},
		{name: "FRINTZS/src=V31,dst=V31", inst: FRINTZS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xc3, 0x25, 0x1e}},
		{name: "FDIVS/src=V0,dst=V0", inst: FDIVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x20, 0x1e}},
		{name: "FDIVS/src=V0,dst=V31", inst: FDIVS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x20, 0x1e}},
		{name: "FDIVS/src=V31,dst=V0", inst: FDIVS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x3f, 0x1e}},
		{name: "FDIVS/src=V31,dst=V31", inst: FDIVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x3f, 0x1e}},
		{name: "FDIVD/src=V0,dst=V0", inst: FDIVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x18, 0x60, 0x1e}},
		{name: "FDIVD/src=V0,dst=V31", inst: FDIVD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x1b, 0x60, 0x1e}},
		{name: "FDIVD/src=V31,dst=V0", inst: FDIVD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x18, 0x7f, 0x1e}},
		{name: "FDIVD/src=V31,dst=V31", inst: FDIVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x1b, 0x7f, 0x1e}},
		{name: "FMAXD/src=V0,dst=V0", inst: FMAXD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x60, 0x1e}},
		{name: "FMAXD/src=V0,dst=V31", inst: FMAXD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x60, 0x1e}},
		{name: "FMAXD/src=V31,dst=V0", inst: FMAXD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x7f, 0x1e}},
		{name: "FMAXD/src=V31,dst=V31", inst: FMAXD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x7f, 0x1e}},
		{name: "FMAXS/src=V0,dst=V0", inst: FMAXS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x48, 0x20, 0x1e}},
		{name: "FMAXS/src=V0,dst=V31", inst: FMAXS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x4b, 0x20, 0x1e}},
		{name: "FMAXS/src=V31,dst=V0", inst: FMAXS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x48, 0x3f, 0x1e}},
		{name: "FMAXS/src=V31,dst=V31", inst: FMAXS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x4b, 0x3f, 0x1e}},
		{name: "FMIND/src=V0,dst=V0", inst: FMIND, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x60, 0x1e}},
		{name: "FMIND/src=V0,dst=V31", inst: FMIND, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x60, 0x1e}},
		{name: "FMIND/src=V31,dst=V0", inst: FMIND, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x7f, 0x1e}},
		{name: "FMIND/src=V31,dst=V31", inst: FMIND, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x7f, 0x1e}},
		{name: "FMINS/src=V0,dst=V0", inst: FMINS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x58, 0x20, 0x1e}},
		{name: "FMINS/src=V0,dst=V31", inst: FMINS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x5b, 0x20, 0x1e}},
		{name: "FMINS/src=V31,dst=V0", inst: FMINS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x58, 0x3f, 0x1e}},
		{name: "FMINS/src=V31,dst=V31", inst: FMINS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x5b, 0x3f, 0x1e}},
		{name: "FMULS/src=V0,dst=V0", inst: FMULS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x20, 0x1e}},
		{name: "FMULS/src=V0,dst=V31", inst: FMULS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x20, 0x1e}},
		{name: "FMULS/src=V31,dst=V0", inst: FMULS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x3f, 0x1e}},
		{name: "FMULS/src=V31,dst=V31", inst: FMULS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x3f, 0x1e}},
		{name: "FMULD/src=V0,dst=V0", inst: FMULD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x8, 0x60, 0x1e}},
		{name: "FMULD/src=V0,dst=V31", inst: FMULD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0xb, 0x60, 0x1e}},
		{name: "FMULD/src=V31,dst=V0", inst: FMULD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x8, 0x7f, 0x1e}},
		{name: "FMULD/src=V31,dst=V31", inst: FMULD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0xb, 0x7f, 0x1e}},
		{name: "FADDD/src=V0,dst=V0", inst: FADDD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x60, 0x1e}},
		{name: "FADDD/src=V0,dst=V31", inst: FADDD, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x60, 0x1e}},
		{name: "FADDD/src=V31,dst=V0", inst: FADDD, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x7f, 0x1e}},
		{name: "FADDD/src=V31,dst=V31", inst: FADDD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x7f, 0x1e}},
		{name: "FADDS/src=V0,dst=V0", inst: FADDS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x28, 0x20, 0x1e}},
		{name: "FADDS/src=V0,dst=V31", inst: FADDS, src: RegV0, dst: RegV31, exp: []byte{0xff, 0x2b, 0x20, 0x1e}},
		{name: "FADDS/src=V31,dst=V0", inst: FADDS, src: RegV31, dst: RegV0, exp: []byte{0x0, 0x28, 0x3f, 0x1e}},
		{name: "FADDS/src=V31,dst=V31", inst: FADDS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x2b, 0x3f, 0x1e}},
		{name: "FCVTZSD/src=V0,dst=RZR", inst: FCVTZSD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x9e}},
		{name: "FCVTZSD/src=V0,dst=R10", inst: FCVTZSD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x9e}},
		{name: "FCVTZSD/src=V0,dst=R30", inst: FCVTZSD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x9e}},
		{name: "FCVTZSD/src=V31,dst=RZR", inst: FCVTZSD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x9e}},
		{name: "FCVTZSD/src=V31,dst=R10", inst: FCVTZSD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x9e}},
		{name: "FCVTZSD/src=V31,dst=R30", inst: FCVTZSD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x9e}},
		{name: "FCVTZSDW/src=V0,dst=RZR", inst: FCVTZSDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x78, 0x1e}},
		{name: "FCVTZSDW/src=V0,dst=R10", inst: FCVTZSDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x78, 0x1e}},
		{name: "FCVTZSDW/src=V0,dst=R30", inst: FCVTZSDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x78, 0x1e}},
		{name: "FCVTZSDW/src=V31,dst=RZR", inst: FCVTZSDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x78, 0x1e}},
		{name: "FCVTZSDW/src=V31,dst=R10", inst: FCVTZSDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x78, 0x1e}},
		{name: "FCVTZSDW/src=V31,dst=R30", inst: FCVTZSDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x78, 0x1e}},
		{name: "FCVTZSS/src=V0,dst=RZR", inst: FCVTZSS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x9e}},
		{name: "FCVTZSS/src=V0,dst=R10", inst: FCVTZSS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x9e}},
		{name: "FCVTZSS/src=V0,dst=R30", inst: FCVTZSS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x9e}},
		{name: "FCVTZSS/src=V31,dst=RZR", inst: FCVTZSS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x9e}},
		{name: "FCVTZSS/src=V31,dst=R10", inst: FCVTZSS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x9e}},
		{name: "FCVTZSS/src=V31,dst=R30", inst: FCVTZSS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x9e}},
		{name: "FCVTZSSW/src=V0,dst=RZR", inst: FCVTZSSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x38, 0x1e}},
		{name: "FCVTZSSW/src=V0,dst=R10", inst: FCVTZSSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x38, 0x1e}},
		{name: "FCVTZSSW/src=V0,dst=R30", inst: FCVTZSSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x38, 0x1e}},
		{name: "FCVTZSSW/src=V31,dst=RZR", inst: FCVTZSSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x38, 0x1e}},
		{name: "FCVTZSSW/src=V31,dst=R10", inst: FCVTZSSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x38, 0x1e}},
		{name: "FCVTZSSW/src=V31,dst=R30", inst: FCVTZSSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x38, 0x1e}},
		{name: "FCVTZUD/src=V0,dst=RZR", inst: FCVTZUD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x9e}},
		{name: "FCVTZUD/src=V0,dst=R10", inst: FCVTZUD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x9e}},
		{name: "FCVTZUD/src=V0,dst=R30", inst: FCVTZUD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x9e}},
		{name: "FCVTZUD/src=V31,dst=RZR", inst: FCVTZUD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x9e}},
		{name: "FCVTZUD/src=V31,dst=R10", inst: FCVTZUD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x9e}},
		{name: "FCVTZUD/src=V31,dst=R30", inst: FCVTZUD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x9e}},
		{name: "FCVTZUDW/src=V0,dst=RZR", inst: FCVTZUDW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x79, 0x1e}},
		{name: "FCVTZUDW/src=V0,dst=R10", inst: FCVTZUDW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x79, 0x1e}},
		{name: "FCVTZUDW/src=V0,dst=R30", inst: FCVTZUDW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x79, 0x1e}},
		{name: "FCVTZUDW/src=V31,dst=RZR", inst: FCVTZUDW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x79, 0x1e}},
		{name: "FCVTZUDW/src=V31,dst=R10", inst: FCVTZUDW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x79, 0x1e}},
		{name: "FCVTZUDW/src=V31,dst=R30", inst: FCVTZUDW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x79, 0x1e}},
		{name: "FCVTZUS/src=V0,dst=RZR", inst: FCVTZUS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x9e}},
		{name: "FCVTZUS/src=V0,dst=R10", inst: FCVTZUS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x9e}},
		{name: "FCVTZUS/src=V0,dst=R30", inst: FCVTZUS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x9e}},
		{name: "FCVTZUS/src=V31,dst=RZR", inst: FCVTZUS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x9e}},
		{name: "FCVTZUS/src=V31,dst=R10", inst: FCVTZUS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x9e}},
		{name: "FCVTZUS/src=V31,dst=R30", inst: FCVTZUS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x9e}},
		{name: "FCVTZUSW/src=V0,dst=RZR", inst: FCVTZUSW, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x39, 0x1e}},
		{name: "FCVTZUSW/src=V0,dst=R10", inst: FCVTZUSW, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x39, 0x1e}},
		{name: "FCVTZUSW/src=V0,dst=R30", inst: FCVTZUSW, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x39, 0x1e}},
		{name: "FCVTZUSW/src=V31,dst=RZR", inst: FCVTZUSW, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x39, 0x1e}},
		{name: "FCVTZUSW/src=V31,dst=R10", inst: FCVTZUSW, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x39, 0x1e}},
		{name: "FCVTZUSW/src=V31,dst=R30", inst: FCVTZUSW, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x39, 0x1e}},
		{name: "FMOVD/src=V0,dst=V0", inst: FMOVD, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x60, 0x1e}},
		{name: "FMOVD/src=V0,dst=V31", inst: FMOVD, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x60, 0x1e}},
		{name: "FMOVD/src=V31,dst=V0", inst: FMOVD, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x60, 0x1e}},
		{name: "FMOVD/src=V31,dst=V31", inst: FMOVD, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x60, 0x1e}},
		{name: "FMOVS/src=V0,dst=V0", inst: FMOVS, src: RegV0, dst: RegV0, exp: []byte{0x0, 0x40, 0x20, 0x1e}},
		{name: "FMOVS/src=V0,dst=V31", inst: FMOVS, src: RegV0, dst: RegV31, exp: []byte{0x1f, 0x40, 0x20, 0x1e}},
		{name: "FMOVS/src=V31,dst=V0", inst: FMOVS, src: RegV31, dst: RegV0, exp: []byte{0xe0, 0x43, 0x20, 0x1e}},
		{name: "FMOVS/src=V31,dst=V31", inst: FMOVS, src: RegV31, dst: RegV31, exp: []byte{0xff, 0x43, 0x20, 0x1e}},
		{name: "FMOVD/src=RZR,dst=V0", inst: FMOVD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x67, 0x9e}},
		{name: "FMOVD/src=RZR,dst=V31", inst: FMOVD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x67, 0x9e}},
		{name: "FMOVD/src=R10,dst=V0", inst: FMOVD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x67, 0x9e}},
		{name: "FMOVD/src=R10,dst=V31", inst: FMOVD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x67, 0x9e}},
		{name: "FMOVD/src=R30,dst=V0", inst: FMOVD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x67, 0x9e}},
		{name: "FMOVD/src=R30,dst=V31", inst: FMOVD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x67, 0x9e}},
		{name: "FMOVS/src=RZR,dst=V0", inst: FMOVS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x27, 0x1e}},
		{name: "FMOVS/src=RZR,dst=V31", inst: FMOVS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x27, 0x1e}},
		{name: "FMOVS/src=R10,dst=V0", inst: FMOVS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x27, 0x1e}},
		{name: "FMOVS/src=R10,dst=V31", inst: FMOVS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x27, 0x1e}},
		{name: "FMOVS/src=R30,dst=V0", inst: FMOVS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x27, 0x1e}},
		{name: "FMOVS/src=R30,dst=V31", inst: FMOVS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x27, 0x1e}},
		{name: "FMOVD/src=V0,dst=RZR", inst: FMOVD, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x66, 0x9e}},
		{name: "FMOVD/src=V0,dst=R10", inst: FMOVD, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x66, 0x9e}},
		{name: "FMOVD/src=V0,dst=R30", inst: FMOVD, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x66, 0x9e}},
		{name: "FMOVD/src=V31,dst=RZR", inst: FMOVD, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x66, 0x9e}},
		{name: "FMOVD/src=V31,dst=R10", inst: FMOVD, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x66, 0x9e}},
		{name: "FMOVD/src=V31,dst=R30", inst: FMOVD, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x66, 0x9e}},
		{name: "FMOVS/src=V0,dst=RZR", inst: FMOVS, src: RegV0, dst: RegRZR, exp: []byte{0x1f, 0x0, 0x26, 0x1e}},
		{name: "FMOVS/src=V0,dst=R10", inst: FMOVS, src: RegV0, dst: RegR10, exp: []byte{0xa, 0x0, 0x26, 0x1e}},
		{name: "FMOVS/src=V0,dst=R30", inst: FMOVS, src: RegV0, dst: RegR30, exp: []byte{0x1e, 0x0, 0x26, 0x1e}},
		{name: "FMOVS/src=V31,dst=RZR", inst: FMOVS, src: RegV31, dst: RegRZR, exp: []byte{0xff, 0x3, 0x26, 0x1e}},
		{name: "FMOVS/src=V31,dst=R10", inst: FMOVS, src: RegV31, dst: RegR10, exp: []byte{0xea, 0x3, 0x26, 0x1e}},
		{name: "FMOVS/src=V31,dst=R30", inst: FMOVS, src: RegV31, dst: RegR30, exp: []byte{0xfe, 0x3, 0x26, 0x1e}},
		{name: "MOVD/src=RZR,dst=R10", inst: MOVD, src: RegRZR, dst: RegR10, exp: []byte{0xa, 0x0, 0x80, 0xd2}},
		{name: "MOVD/src=RZR,dst=R30", inst: MOVD, src: RegRZR, dst: RegR30, exp: []byte{0x1e, 0x0, 0x80, 0xd2}},
		{name: "MOVD/src=R10,dst=R10", inst: MOVD, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xaa}},
		{name: "MOVD/src=R10,dst=R30", inst: MOVD, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xaa}},
		{name: "MOVD/src=R30,dst=R10", inst: MOVD, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xaa}},
		{name: "MOVD/src=R30,dst=R30", inst: MOVD, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xaa}},
		{name: "MRS/src=FPSR,dst=RZR", inst: MRS, src: RegFPSR, dst: RegRZR, exp: []byte{0x3f, 0x44, 0x3b, 0xd5}},
		{name: "MRS/src=FPSR,dst=R10", inst: MRS, src: RegFPSR, dst: RegR10, exp: []byte{0x2a, 0x44, 0x3b, 0xd5}},
		{name: "MRS/src=FPSR,dst=R30", inst: MRS, src: RegFPSR, dst: RegR30, exp: []byte{0x3e, 0x44, 0x3b, 0xd5}},
		{name: "MSR/src=RZR,dst=FPSR", inst: MSR, src: RegRZR, dst: RegFPSR, exp: []byte{0x3f, 0x44, 0x1b, 0xd5}},
		{name: "MSR/src=R10,dst=FPSR", inst: MSR, src: RegR10, dst: RegFPSR, exp: []byte{0x2a, 0x44, 0x1b, 0xd5}},
		{name: "MSR/src=R30,dst=FPSR", inst: MSR, src: RegR30, dst: RegFPSR, exp: []byte{0x3e, 0x44, 0x1b, 0xd5}},
		{name: "MUL/src=RZR,dst=RZR", inst: MUL, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x9b}},
		{name: "MUL/src=RZR,dst=R10", inst: MUL, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x9b}},
		{name: "MUL/src=RZR,dst=R30", inst: MUL, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x9b}},
		{name: "MUL/src=R10,dst=RZR", inst: MUL, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x9b}},
		{name: "MUL/src=R10,dst=R10", inst: MUL, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x9b}},
		{name: "MUL/src=R10,dst=R30", inst: MUL, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x9b}},
		{name: "MUL/src=R30,dst=RZR", inst: MUL, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x9b}},
		{name: "MUL/src=R30,dst=R10", inst: MUL, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x9b}},
		{name: "MUL/src=R30,dst=R30", inst: MUL, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x9b}},
		{name: "MULW/src=RZR,dst=RZR", inst: MULW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1f, 0x1b}},
		{name: "MULW/src=RZR,dst=R10", inst: MULW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1f, 0x1b}},
		{name: "MULW/src=RZR,dst=R30", inst: MULW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1f, 0x1b}},
		{name: "MULW/src=R10,dst=RZR", inst: MULW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x7f, 0xa, 0x1b}},
		{name: "MULW/src=R10,dst=R10", inst: MULW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0xa, 0x1b}},
		{name: "MULW/src=R10,dst=R30", inst: MULW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0x7f, 0xa, 0x1b}},
		{name: "MULW/src=R30,dst=RZR", inst: MULW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x7f, 0x1e, 0x1b}},
		{name: "MULW/src=R30,dst=R10", inst: MULW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x1e, 0x1b}},
		{name: "MULW/src=R30,dst=R30", inst: MULW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x1e, 0x1b}},
		{name: "NEG/src=RZR,dst=RZR", inst: NEG, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0xcb}},
		{name: "NEG/src=RZR,dst=R10", inst: NEG, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0xcb}},
		{name: "NEG/src=RZR,dst=R30", inst: NEG, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0xcb}},
		{name: "NEG/src=R10,dst=RZR", inst: NEG, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0xcb}},
		{name: "NEG/src=R10,dst=R10", inst: NEG, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0xcb}},
		{name: "NEG/src=R10,dst=R30", inst: NEG, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0xcb}},
		{name: "NEG/src=R30,dst=RZR", inst: NEG, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0xcb}},
		{name: "NEG/src=R30,dst=R10", inst: NEG, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0xcb}},
		{name: "NEG/src=R30,dst=R30", inst: NEG, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0xcb}},
		{name: "NEGW/src=RZR,dst=RZR", inst: NEGW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x4b}},
		{name: "NEGW/src=RZR,dst=R10", inst: NEGW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x4b}},
		{name: "NEGW/src=RZR,dst=R30", inst: NEGW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x4b}},
		{name: "NEGW/src=R10,dst=RZR", inst: NEGW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0x3, 0xa, 0x4b}},
		{name: "NEGW/src=R10,dst=R10", inst: NEGW, src: RegR10, dst: RegR10, exp: []byte{0xea, 0x3, 0xa, 0x4b}},
		{name: "NEGW/src=R10,dst=R30", inst: NEGW, src: RegR10, dst: RegR30, exp: []byte{0xfe, 0x3, 0xa, 0x4b}},
		{name: "NEGW/src=R30,dst=RZR", inst: NEGW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1e, 0x4b}},
		{name: "NEGW/src=R30,dst=R10", inst: NEGW, src: RegR30, dst: RegR10, exp: []byte{0xea, 0x3, 0x1e, 0x4b}},
		{name: "NEGW/src=R30,dst=R30", inst: NEGW, src: RegR30, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1e, 0x4b}},
		{name: "RBIT/src=RZR,dst=RZR", inst: RBIT, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0xda}},
		{name: "RBIT/src=RZR,dst=R10", inst: RBIT, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0xda}},
		{name: "RBIT/src=RZR,dst=R30", inst: RBIT, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0xda}},
		{name: "RBIT/src=R10,dst=RZR", inst: RBIT, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0xda}},
		{name: "RBIT/src=R10,dst=R10", inst: RBIT, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0xda}},
		{name: "RBIT/src=R10,dst=R30", inst: RBIT, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0xda}},
		{name: "RBIT/src=R30,dst=RZR", inst: RBIT, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0xda}},
		{name: "RBIT/src=R30,dst=R10", inst: RBIT, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0xda}},
		{name: "RBIT/src=R30,dst=R30", inst: RBIT, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0xda}},
		{name: "RBITW/src=RZR,dst=RZR", inst: RBITW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0xc0, 0x5a}},
		{name: "RBITW/src=RZR,dst=R10", inst: RBITW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0xc0, 0x5a}},
		{name: "RBITW/src=RZR,dst=R30", inst: RBITW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0xc0, 0x5a}},
		{name: "RBITW/src=R10,dst=RZR", inst: RBITW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1, 0xc0, 0x5a}},
		{name: "RBITW/src=R10,dst=R10", inst: RBITW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1, 0xc0, 0x5a}},
		{name: "RBITW/src=R10,dst=R30", inst: RBITW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1, 0xc0, 0x5a}},
		{name: "RBITW/src=R30,dst=RZR", inst: RBITW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3, 0xc0, 0x5a}},
		{name: "RBITW/src=R30,dst=R10", inst: RBITW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3, 0xc0, 0x5a}},
		{name: "RBITW/src=R30,dst=R30", inst: RBITW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3, 0xc0, 0x5a}},
		{name: "SDIV/src=RZR,dst=RZR", inst: SDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x9a}},
		{name: "SDIV/src=RZR,dst=R10", inst: SDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x9a}},
		{name: "SDIV/src=RZR,dst=R30", inst: SDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x9a}},
		{name: "SDIV/src=R10,dst=RZR", inst: SDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x9a}},
		{name: "SDIV/src=R10,dst=R10", inst: SDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x9a}},
		{name: "SDIV/src=R10,dst=R30", inst: SDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x9a}},
		{name: "SDIV/src=R30,dst=RZR", inst: SDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x9a}},
		{name: "SDIV/src=R30,dst=R10", inst: SDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x9a}},
		{name: "SDIV/src=R30,dst=R30", inst: SDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x9a}},
		{name: "SDIVW/src=RZR,dst=RZR", inst: SDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xf, 0xdf, 0x1a}},
		{name: "SDIVW/src=RZR,dst=R10", inst: SDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0xd, 0xdf, 0x1a}},
		{name: "SDIVW/src=RZR,dst=R30", inst: SDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xf, 0xdf, 0x1a}},
		{name: "SDIVW/src=R10,dst=RZR", inst: SDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xf, 0xca, 0x1a}},
		{name: "SDIVW/src=R10,dst=R10", inst: SDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0xd, 0xca, 0x1a}},
		{name: "SDIVW/src=R10,dst=R30", inst: SDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xf, 0xca, 0x1a}},
		{name: "SDIVW/src=R30,dst=RZR", inst: SDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xf, 0xde, 0x1a}},
		{name: "SDIVW/src=R30,dst=R10", inst: SDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0xd, 0xde, 0x1a}},
		{name: "SDIVW/src=R30,dst=R30", inst: SDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xf, 0xde, 0x1a}},
		{name: "UDIV/src=RZR,dst=RZR", inst: UDIV, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x9a}},
		{name: "UDIV/src=RZR,dst=R10", inst: UDIV, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x9a}},
		{name: "UDIV/src=RZR,dst=R30", inst: UDIV, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x9a}},
		{name: "UDIV/src=R10,dst=RZR", inst: UDIV, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x9a}},
		{name: "UDIV/src=R10,dst=R10", inst: UDIV, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x9a}},
		{name: "UDIV/src=R10,dst=R30", inst: UDIV, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x9a}},
		{name: "UDIV/src=R30,dst=RZR", inst: UDIV, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x9a}},
		{name: "UDIV/src=R30,dst=R10", inst: UDIV, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x9a}},
		{name: "UDIV/src=R30,dst=R30", inst: UDIV, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x9a}},
		{name: "UDIVW/src=RZR,dst=RZR", inst: UDIVW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0xb, 0xdf, 0x1a}},
		{name: "UDIVW/src=RZR,dst=R10", inst: UDIVW, src: RegRZR, dst: RegR10, exp: []byte{0x4a, 0x9, 0xdf, 0x1a}},
		{name: "UDIVW/src=RZR,dst=R30", inst: UDIVW, src: RegRZR, dst: RegR30, exp: []byte{0xde, 0xb, 0xdf, 0x1a}},
		{name: "UDIVW/src=R10,dst=RZR", inst: UDIVW, src: RegR10, dst: RegRZR, exp: []byte{0xff, 0xb, 0xca, 0x1a}},
		{name: "UDIVW/src=R10,dst=R10", inst: UDIVW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x9, 0xca, 0x1a}},
		{name: "UDIVW/src=R10,dst=R30", inst: UDIVW, src: RegR10, dst: RegR30, exp: []byte{0xde, 0xb, 0xca, 0x1a}},
		{name: "UDIVW/src=R30,dst=RZR", inst: UDIVW, src: RegR30, dst: RegRZR, exp: []byte{0xff, 0xb, 0xde, 0x1a}},
		{name: "UDIVW/src=R30,dst=R10", inst: UDIVW, src: RegR30, dst: RegR10, exp: []byte{0x4a, 0x9, 0xde, 0x1a}},
		{name: "UDIVW/src=R30,dst=R30", inst: UDIVW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0xb, 0xde, 0x1a}},
		{name: "SCVTFD/src=RZR,dst=V0", inst: SCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x9e}},
		{name: "SCVTFD/src=RZR,dst=V31", inst: SCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x9e}},
		{name: "SCVTFD/src=R10,dst=V0", inst: SCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x9e}},
		{name: "SCVTFD/src=R10,dst=V31", inst: SCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x9e}},
		{name: "SCVTFD/src=R30,dst=V0", inst: SCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x9e}},
		{name: "SCVTFD/src=R30,dst=V31", inst: SCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x9e}},
		{name: "SCVTFWD/src=RZR,dst=V0", inst: SCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x62, 0x1e}},
		{name: "SCVTFWD/src=RZR,dst=V31", inst: SCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x62, 0x1e}},
		{name: "SCVTFWD/src=R10,dst=V0", inst: SCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x62, 0x1e}},
		{name: "SCVTFWD/src=R10,dst=V31", inst: SCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x62, 0x1e}},
		{name: "SCVTFWD/src=R30,dst=V0", inst: SCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x62, 0x1e}},
		{name: "SCVTFWD/src=R30,dst=V31", inst: SCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x62, 0x1e}},
		{name: "SCVTFS/src=RZR,dst=V0", inst: SCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x9e}},
		{name: "SCVTFS/src=RZR,dst=V31", inst: SCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x9e}},
		{name: "SCVTFS/src=R10,dst=V0", inst: SCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x9e}},
		{name: "SCVTFS/src=R10,dst=V31", inst: SCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x9e}},
		{name: "SCVTFS/src=R30,dst=V0", inst: SCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x9e}},
		{name: "SCVTFS/src=R30,dst=V31", inst: SCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x9e}},
		{name: "SCVTFWS/src=RZR,dst=V0", inst: SCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x22, 0x1e}},
		{name: "SCVTFWS/src=RZR,dst=V31", inst: SCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x22, 0x1e}},
		{name: "SCVTFWS/src=R10,dst=V0", inst: SCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x22, 0x1e}},
		{name: "SCVTFWS/src=R10,dst=V31", inst: SCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x22, 0x1e}},
		{name: "SCVTFWS/src=R30,dst=V0", inst: SCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x22, 0x1e}},
		{name: "SCVTFWS/src=R30,dst=V31", inst: SCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x22, 0x1e}},
		{name: "UCVTFD/src=RZR,dst=V0", inst: UCVTFD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x9e}},
		{name: "UCVTFD/src=RZR,dst=V31", inst: UCVTFD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x9e}},
		{name: "UCVTFD/src=R10,dst=V0", inst: UCVTFD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x9e}},
		{name: "UCVTFD/src=R10,dst=V31", inst: UCVTFD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x9e}},
		{name: "UCVTFD/src=R30,dst=V0", inst: UCVTFD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x9e}},
		{name: "UCVTFD/src=R30,dst=V31", inst: UCVTFD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x9e}},
		{name: "UCVTFWD/src=RZR,dst=V0", inst: UCVTFWD, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x63, 0x1e}},
		{name: "UCVTFWD/src=RZR,dst=V31", inst: UCVTFWD, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x63, 0x1e}},
		{name: "UCVTFWD/src=R10,dst=V0", inst: UCVTFWD, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x63, 0x1e}},
		{name: "UCVTFWD/src=R10,dst=V31", inst: UCVTFWD, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x63, 0x1e}},
		{name: "UCVTFWD/src=R30,dst=V0", inst: UCVTFWD, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x63, 0x1e}},
		{name: "UCVTFWD/src=R30,dst=V31", inst: UCVTFWD, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x63, 0x1e}},
		{name: "UCVTFS/src=RZR,dst=V0", inst: UCVTFS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x9e}},
		{name: "UCVTFS/src=RZR,dst=V31", inst: UCVTFS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x9e}},
		{name: "UCVTFS/src=R10,dst=V0", inst: UCVTFS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x9e}},
		{name: "UCVTFS/src=R10,dst=V31", inst: UCVTFS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x9e}},
		{name: "UCVTFS/src=R30,dst=V0", inst: UCVTFS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x9e}},
		{name: "UCVTFS/src=R30,dst=V31", inst: UCVTFS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x9e}},
		{name: "UCVTFWS/src=RZR,dst=V0", inst: UCVTFWS, src: RegRZR, dst: RegV0, exp: []byte{0xe0, 0x3, 0x23, 0x1e}},
		{name: "UCVTFWS/src=RZR,dst=V31", inst: UCVTFWS, src: RegRZR, dst: RegV31, exp: []byte{0xff, 0x3, 0x23, 0x1e}},
		{name: "UCVTFWS/src=R10,dst=V0", inst: UCVTFWS, src: RegR10, dst: RegV0, exp: []byte{0x40, 0x1, 0x23, 0x1e}},
		{name: "UCVTFWS/src=R10,dst=V31", inst: UCVTFWS, src: RegR10, dst: RegV31, exp: []byte{0x5f, 0x1, 0x23, 0x1e}},
		{name: "UCVTFWS/src=R30,dst=V0", inst: UCVTFWS, src: RegR30, dst: RegV0, exp: []byte{0xc0, 0x3, 0x23, 0x1e}},
		{name: "UCVTFWS/src=R30,dst=V31", inst: UCVTFWS, src: RegR30, dst: RegV31, exp: []byte{0xdf, 0x3, 0x23, 0x1e}},
		{name: "SXTB/src=RZR,dst=RZR", inst: SXTB, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "SXTB/src=RZR,dst=R10", inst: SXTB, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "SXTB/src=RZR,dst=R30", inst: SXTB, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "SXTB/src=R10,dst=RZR", inst: SXTB, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x40, 0x93}},
		{name: "SXTB/src=R10,dst=R10", inst: SXTB, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x40, 0x93}},
		{name: "SXTB/src=R10,dst=R30", inst: SXTB, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x40, 0x93}},
		{name: "SXTB/src=R30,dst=RZR", inst: SXTB, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x40, 0x93}},
		{name: "SXTB/src=R30,dst=R10", inst: SXTB, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x40, 0x93}},
		{name: "SXTB/src=R30,dst=R30", inst: SXTB, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x40, 0x93}},
		{name: "SXTBW/src=RZR,dst=RZR", inst: SXTBW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "SXTBW/src=RZR,dst=R10", inst: SXTBW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "SXTBW/src=RZR,dst=R30", inst: SXTBW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "SXTBW/src=R10,dst=RZR", inst: SXTBW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x1d, 0x0, 0x13}},
		{name: "SXTBW/src=R10,dst=R10", inst: SXTBW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x1d, 0x0, 0x13}},
		{name: "SXTBW/src=R10,dst=R30", inst: SXTBW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x1d, 0x0, 0x13}},
		{name: "SXTBW/src=R30,dst=RZR", inst: SXTBW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x1f, 0x0, 0x13}},
		{name: "SXTBW/src=R30,dst=R10", inst: SXTBW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x1f, 0x0, 0x13}},
		{name: "SXTBW/src=R30,dst=R30", inst: SXTBW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x1f, 0x0, 0x13}},
		{name: "SXTH/src=RZR,dst=RZR", inst: SXTH, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "SXTH/src=RZR,dst=R10", inst: SXTH, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "SXTH/src=RZR,dst=R30", inst: SXTH, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "SXTH/src=R10,dst=RZR", inst: SXTH, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x40, 0x93}},
		{name: "SXTH/src=R10,dst=R10", inst: SXTH, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x40, 0x93}},
		{name: "SXTH/src=R10,dst=R30", inst: SXTH, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x40, 0x93}},
		{name: "SXTH/src=R30,dst=RZR", inst: SXTH, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x40, 0x93}},
		{name: "SXTH/src=R30,dst=R10", inst: SXTH, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x40, 0x93}},
		{name: "SXTH/src=R30,dst=R30", inst: SXTH, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x40, 0x93}},
		{name: "SXTHW/src=RZR,dst=RZR", inst: SXTHW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "SXTHW/src=RZR,dst=R10", inst: SXTHW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "SXTHW/src=RZR,dst=R30", inst: SXTHW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "SXTHW/src=R10,dst=RZR", inst: SXTHW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x3d, 0x0, 0x13}},
		{name: "SXTHW/src=R10,dst=R10", inst: SXTHW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x3d, 0x0, 0x13}},
		{name: "SXTHW/src=R10,dst=R30", inst: SXTHW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x3d, 0x0, 0x13}},
		{name: "SXTHW/src=R30,dst=RZR", inst: SXTHW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x3f, 0x0, 0x13}},
		{name: "SXTHW/src=R30,dst=R10", inst: SXTHW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x3f, 0x0, 0x13}},
		{name: "SXTHW/src=R30,dst=R30", inst: SXTHW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x3f, 0x0, 0x13}},
		{name: "SXTW/src=RZR,dst=RZR", inst: SXTW, src: RegRZR, dst: RegRZR, exp: []byte{0xff, 0x3, 0x1f, 0x2a}},
		{name: "SXTW/src=RZR,dst=R10", inst: SXTW, src: RegRZR, dst: RegR10, exp: []byte{0xea, 0x3, 0x1f, 0x2a}},
		{name: "SXTW/src=RZR,dst=R30", inst: SXTW, src: RegRZR, dst: RegR30, exp: []byte{0xfe, 0x3, 0x1f, 0x2a}},
		{name: "SXTW/src=R10,dst=RZR", inst: SXTW, src: RegR10, dst: RegRZR, exp: []byte{0x5f, 0x7d, 0x40, 0x93}},
		{name: "SXTW/src=R10,dst=R10", inst: SXTW, src: RegR10, dst: RegR10, exp: []byte{0x4a, 0x7d, 0x40, 0x93}},
		{name: "SXTW/src=R10,dst=R30", inst: SXTW, src: RegR10, dst: RegR30, exp: []byte{0x5e, 0x7d, 0x40, 0x93}},
		{name: "SXTW/src=R30,dst=RZR", inst: SXTW, src: RegR30, dst: RegRZR, exp: []byte{0xdf, 0x7f, 0x40, 0x93}},
		{name: "SXTW/src=R30,dst=R10", inst: SXTW, src: RegR30, dst: RegR10, exp: []byte{0xca, 0x7f, 0x40, 0x93}},
		{name: "SXTW/src=R30,dst=R30", inst: SXTW, src: RegR30, dst: RegR30, exp: []byte{0xde, 0x7f, 0x40, 0x93}},
	}

	for _, tc := range tests {
		t.Run(tc.name, func(t *testing.T) {
			a := NewAssembler(asm.NilRegister)
			err := a.encodeRegisterToRegister(&nodeImpl{instruction: tc.inst, srcReg: tc.src, dstReg: tc.dst})
			require.NoError(t, err)

			actual := a.buf.Bytes()
			require.Equal(t, tc.exp, actual[:4], hex.EncodeToString(actual[:4]))
		})
	}
}
