// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT

pub const tricoreConst = enum(c_int) {

// TRICORE CPU

	CPU_TRICORE_TC1796 = 0,
	CPU_TRICORE_TC1797 = 1,
	CPU_TRICORE_TC27X = 2,
	CPU_TRICORE_ENDING = 3,

// TRICORE registers

	TRICORE_REG_INVALID = 0,
	TRICORE_REG_A0 = 1,
	TRICORE_REG_A1 = 2,
	TRICORE_REG_A2 = 3,
	TRICORE_REG_A3 = 4,
	TRICORE_REG_A4 = 5,
	TRICORE_REG_A5 = 6,
	TRICORE_REG_A6 = 7,
	TRICORE_REG_A7 = 8,
	TRICORE_REG_A8 = 9,
	TRICORE_REG_A9 = 10,
	TRICORE_REG_A10 = 11,
	TRICORE_REG_A11 = 12,
	TRICORE_REG_A12 = 13,
	TRICORE_REG_A13 = 14,
	TRICORE_REG_A14 = 15,
	TRICORE_REG_A15 = 16,
	TRICORE_REG_D0 = 17,
	TRICORE_REG_D1 = 18,
	TRICORE_REG_D2 = 19,
	TRICORE_REG_D3 = 20,
	TRICORE_REG_D4 = 21,
	TRICORE_REG_D5 = 22,
	TRICORE_REG_D6 = 23,
	TRICORE_REG_D7 = 24,
	TRICORE_REG_D8 = 25,
	TRICORE_REG_D9 = 26,
	TRICORE_REG_D10 = 27,
	TRICORE_REG_D11 = 28,
	TRICORE_REG_D12 = 29,
	TRICORE_REG_D13 = 30,
	TRICORE_REG_D14 = 31,
	TRICORE_REG_D15 = 32,
	TRICORE_REG_PCXI = 33,
	TRICORE_REG_PSW = 34,
	TRICORE_REG_PSW_USB_C = 35,
	TRICORE_REG_PSW_USB_V = 36,
	TRICORE_REG_PSW_USB_SV = 37,
	TRICORE_REG_PSW_USB_AV = 38,
	TRICORE_REG_PSW_USB_SAV = 39,
	TRICORE_REG_PC = 40,
	TRICORE_REG_SYSCON = 41,
	TRICORE_REG_CPU_ID = 42,
	TRICORE_REG_BIV = 43,
	TRICORE_REG_BTV = 44,
	TRICORE_REG_ISP = 45,
	TRICORE_REG_ICR = 46,
	TRICORE_REG_FCX = 47,
	TRICORE_REG_LCX = 48,
	TRICORE_REG_COMPAT = 49,
	TRICORE_REG_DPR0_U = 50,
	TRICORE_REG_DPR1_U = 51,
	TRICORE_REG_DPR2_U = 52,
	TRICORE_REG_DPR3_U = 53,
	TRICORE_REG_DPR0_L = 54,
	TRICORE_REG_DPR1_L = 55,
	TRICORE_REG_DPR2_L = 56,
	TRICORE_REG_DPR3_L = 57,
	TRICORE_REG_CPR0_U = 58,
	TRICORE_REG_CPR1_U = 59,
	TRICORE_REG_CPR2_U = 60,
	TRICORE_REG_CPR3_U = 61,
	TRICORE_REG_CPR0_L = 62,
	TRICORE_REG_CPR1_L = 63,
	TRICORE_REG_CPR2_L = 64,
	TRICORE_REG_CPR3_L = 65,
	TRICORE_REG_DPM0 = 66,
	TRICORE_REG_DPM1 = 67,
	TRICORE_REG_DPM2 = 68,
	TRICORE_REG_DPM3 = 69,
	TRICORE_REG_CPM0 = 70,
	TRICORE_REG_CPM1 = 71,
	TRICORE_REG_CPM2 = 72,
	TRICORE_REG_CPM3 = 73,
	TRICORE_REG_MMU_CON = 74,
	TRICORE_REG_MMU_ASI = 75,
	TRICORE_REG_MMU_TVA = 76,
	TRICORE_REG_MMU_TPA = 77,
	TRICORE_REG_MMU_TPX = 78,
	TRICORE_REG_MMU_TFA = 79,
	TRICORE_REG_BMACON = 80,
	TRICORE_REG_SMACON = 81,
	TRICORE_REG_DIEAR = 82,
	TRICORE_REG_DIETR = 83,
	TRICORE_REG_CCDIER = 84,
	TRICORE_REG_MIECON = 85,
	TRICORE_REG_PIEAR = 86,
	TRICORE_REG_PIETR = 87,
	TRICORE_REG_CCPIER = 88,
	TRICORE_REG_DBGSR = 89,
	TRICORE_REG_EXEVT = 90,
	TRICORE_REG_CREVT = 91,
	TRICORE_REG_SWEVT = 92,
	TRICORE_REG_TR0EVT = 93,
	TRICORE_REG_TR1EVT = 94,
	TRICORE_REG_DMS = 95,
	TRICORE_REG_DCX = 96,
	TRICORE_REG_DBGTCR = 97,
	TRICORE_REG_CCTRL = 98,
	TRICORE_REG_CCNT = 99,
	TRICORE_REG_ICNT = 100,
	TRICORE_REG_M1CNT = 101,
	TRICORE_REG_M2CNT = 102,
	TRICORE_REG_M3CNT = 103,
	TRICORE_REG_ENDING = 104,
	TRICORE_REG_GA0 = 1,
	TRICORE_REG_GA1 = 2,
	TRICORE_REG_GA8 = 9,
	TRICORE_REG_GA9 = 10,
	TRICORE_REG_SP = 11,
	TRICORE_REG_LR = 12,
	TRICORE_REG_IA = 16,
	TRICORE_REG_ID = 32,

};
