* SRDT test
sysclear
archmode esame
r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
r 1d0=0002000180000000000000000000DEAD # z/Arch pgm new PSW
r 200=B7000310     # LCTL R0,R0,CTLR0  Set CR0 bit 45
r 204=41000006     # LA R0,6           R0=Number of test data
r 208=41100380     # LA R1,TEST1       R1=>Test data table
r 20C=41F00400     # LA R15,RES1       R15=>Result table
r 210=68601000     #A LD F6,0(,R1)     Load FPR6=TESTn
r 214=41200004     # LA R2,4           R2=Number of shift tests
r 218=41300318     # LA R3,N1          R3=>Shift count table
r 21C=58403000     #B L R4,0(,R3)      Load R4=Nn
r 220=ED6040008040 # SLDT F8,F6,0      Shift FPR6 left Nn digits
r 226=6080F000     # STD F8,0(,R15)    Store F8 in result table
r 22A=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 22E=B3E200E8     # CUDTR R14,F8      Convert to BCD R14 from FPR8
r 232=E3E0F0000024 # STG R14,0(,R15)   Store R14 in result table
r 238=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 23C=ED6040008041 # SRDT F8,F6,0      Shift FPR6 right Nn digits
r 242=6080F000     # STD F8,0(,R15)    Store F8 in result table
r 246=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 24A=B3E200E8     # CUDTR R14,F8      Convert to BCD R14 from FPR8
r 24E=E3E0F0000024 # STG R14,0(,R15)   Store R14 in result table
r 254=41F0F008     # LA R15,8(,R15)    R15=>next result table
r 258=41303004     # LA R3,4(,R3)      R3=>Next Nn
r 25C=4620021C     # BCT R2,B          Loop to end of Nn table
r 260=41101008     # LA R1,8(,R1)      R1=>Next TESTn
r 264=46000210     # BCT R0,A          Loop to end of TESTn table
r 268=B2B20300     # LPSWE WAITPSW     Load enabled wait PSW
r 300=07020001800000000000000000FED0D0 # WAITPSW Enabled wait state PSW
r 310=00040000     # CTLR0             Control register 0 (bit45 AFP control)
r 314=00000000     # FPCREG            Floating point control register
r 318=00000000     # N1 DC F'0'    Shift count 0
r 31C=FFFFFFC1     # N2 DC F'1'    Shift count 1
r 320=000002C4     # N3 DC F'708'  Shift count 4
r 324=0000003F     # N4 DC F'63'   Shift count 63
r 380=2238000000000000 # TEST1 DC DD'0' Zero positive
r 388=2238000012045078 # TEST2 DC DD'12045078' Normal positive
r 390=ABCDEF0123456789 # TEST3 DC DD'2.989004434259709E116' Large positive
r 398=7CABCDEF01234567 # TEST4 DC DD'QNAN' QNaN positive
r 3A0=FE0000000000ABCD # TEST5 DC DD'-SNAN' SNaN negative
r 3A8=78123456789ABCDE # TEST6 DC DD'INF' Infinity positive
restart
pause 1
* Display test data
r 318.10
r 380.30
* Display results
r 400.300
