#
# This software is Copyright (c) 2016,2019 Denis Burykin
# [denis_burykin yahoo com], [denis-burykin2014 yandex ru]
# and it is hereby released to the general public under the following terms:
# Redistribution and use in source and binary forms, with or without
# modification, are permitted.
#
#####################################################################

AREA_GROUP "input0" RANGE=SLICE_X122Y79:SLICE_X127Y93;
AREA_GROUP "input0" RANGE=RAMB16_X5Y0:RAMB16_X5Y94; # 48
INST "input_fifo/fifo_16in_8out*" AREA_GROUP="input0";

AREA_GROUP "pkt_comm" RANGE=SLICE_X54Y75:SLICE_X73Y100,SLICE_X94Y79:SLICE_X121Y93;
AREA_GROUP "pkt_comm" RANGE=RAMB16_X4Y38:RAMB16_X4Y46; # 5 (req. 2)
AREA_GROUP "pkt_comm" RANGE=RAMB8_X4Y38:RAMB8_X4Y47;
INST "pkt_comm/inpkt_header/*" AREA_GROUP = "pkt_comm";
INST "pkt_comm/word_list/*" AREA_GROUP = "pkt_comm";
INST "pkt_comm/word_distrib/*" AREA_GROUP = "pkt_comm";
INST "pkt_comm/cmp_config/*" AREA_GROUP = "pkt_comm";
INST "pkt_comm/cmp_config_distrib/*" AREA_GROUP = "pkt_comm";
INST "pkt_comm/outpkt_join/*" AREA_GROUP = "pkt_comm";
INST "input_fifo/fifo_input1*" AREA_GROUP="pkt_comm";
INST "output_fifo/*" AREA_GROUP = "pkt_comm";
INST "hs_io_inst/*" AREA_GROUP="pkt_comm";
INST "vcr_inst" AREA_GROUP="pkt_comm";

AREA_GROUP "unit0" RANGE=SLICE_X34Y74:SLICE_X53Y101;
AREA_GROUP "unit0" RANGE=RAMB16_X2Y38:RAMB16_X2Y48; # 6 (req. 3 arbiter + 2 word_gen)
AREA_GROUP "unit0" RANGE=RAMB8_X2Y38:RAMB8_X2Y49;
INST "pkt_comm/units[0].unit/*" AREA_GROUP = "unit0";

AREA_GROUP "unit1" RANGE=SLICE_X74Y74:SLICE_X93Y101;
AREA_GROUP "unit1" RANGE=RAMB16_X3Y38:RAMB16_X3Y48; # 6 (req. 3 arbiter + 2 word_gen)
AREA_GROUP "unit1" RANGE=RAMB8_X3Y38:RAMB8_X3Y49;
INST "pkt_comm/units[1].unit/*" AREA_GROUP = "unit1";

// ------------------------------------------------------------
# Wrapper 0 - Top left (unit #0)
// ------------------------------------------------------------
#
AREA_GROUP "wrapper0_in_r1" RANGE=SLICE_X30Y103:SLICE_X33Y106;
INST "pkt_comm/wrappers[0].wrapper/*in_r1*" AREA_GROUP="wrapper0_in_r1";
AREA_GROUP "wrapper0_in_r2" RANGE=SLICE_X30Y143:SLICE_X33Y155;
INST "pkt_comm/wrappers[0].wrapper/*in_r2*" AREA_GROUP="wrapper0_in_r2";
INST "pkt_comm/wrappers[0].wrapper/*out_r2*" AREA_GROUP="wrapper0_in_r2";
#
# left column 
AREA_GROUP "core0_0" RANGE=SLICE_X0Y173:SLICE_X33Y191;
AREA_GROUP "core0_0" RANGE=RAMB16_X0Y88:RAMB16_X1Y94;
AREA_GROUP "core0_1" RANGE=SLICE_X0Y154:SLICE_X29Y172; # 30x19
AREA_GROUP "core0_1" RANGE=RAMB16_X0Y78:RAMB16_X1Y84;
AREA_GROUP "core0_2" RANGE=SLICE_X0Y135:SLICE_X29Y153; # 30x19
AREA_GROUP "core0_2" RANGE=RAMB16_X0Y68:RAMB16_X1Y74;
AREA_GROUP "core0_3" RANGE=SLICE_X0Y116:SLICE_X29Y134; # 30x19
AREA_GROUP "core0_3" RANGE=RAMB16_X0Y58:RAMB16_X1Y64;
AREA_GROUP "core0_4" RANGE=SLICE_X0Y97:SLICE_X29Y115; # 30x19
AREA_GROUP "core0_4" RANGE=RAMB16_X0Y50:RAMB16_X1Y56;
#
# center-left column
AREA_GROUP "core0_5" RANGE=SLICE_X34Y144:SLICE_X63Y159,SLICE_X48Y160:SLICE_X63Y168;
AREA_GROUP "core0_5" RANGE=RAMB16_X2Y72:RAMB16_X2Y78;
AREA_GROUP "core0_6" RANGE=SLICE_X34Y125:SLICE_X63Y143; # 30x19
AREA_GROUP "core0_6" RANGE=RAMB16_X2Y64:RAMB16_X2Y70;
AREA_GROUP "core0_7" RANGE=SLICE_X34Y106:SLICE_X63Y124; # 30x19
AREA_GROUP "core0_7" RANGE=RAMB16_X2Y54:RAMB16_X2Y60;

// ------------------------------------------------------------
# Wrapper 1 - Bottom Left (unit #0)
// ------------------------------------------------------------
#
AREA_GROUP "wrapper1_in_r1" RANGE=SLICE_X30Y73:SLICE_X33Y79; # ?
INST "pkt_comm/wrappers[1].wrapper/*in_r1*" AREA_GROUP="wrapper1_in_r1";
AREA_GROUP "wrapper1_in_r2" RANGE=SLICE_X30Y37:SLICE_X33Y55;
INST "pkt_comm/wrappers[1].wrapper/*in_r2*" AREA_GROUP="wrapper1_in_r2";
INST "pkt_comm/wrappers[1].wrapper/*out_r2*" AREA_GROUP="wrapper1_in_r2";
#
# left column
AREA_GROUP "core1_0" RANGE=SLICE_X0Y2:SLICE_X33Y19; # 34x18
AREA_GROUP "core1_0" RANGE=RAMB16_X0Y2:RAMB16_X1Y8;
AREA_GROUP "core1_1" RANGE=SLICE_X0Y20:SLICE_X29Y38; # 30x19
AREA_GROUP "core1_1" RANGE=RAMB16_X0Y10:RAMB16_X1Y16;
AREA_GROUP "core1_2" RANGE=SLICE_X0Y39:SLICE_X29Y57;
AREA_GROUP "core1_2" RANGE=RAMB16_X0Y20:RAMB16_X1Y26;
AREA_GROUP "core1_3" RANGE=SLICE_X0Y58:SLICE_X29Y76;
AREA_GROUP "core1_3" RANGE=RAMB16_X0Y28:RAMB16_X1Y36;
AREA_GROUP "core1_4" RANGE=SLICE_X0Y77:SLICE_X29Y95;
AREA_GROUP "core1_4" RANGE=RAMB16_X0Y38:RAMB16_X1Y44;
#
# center-left column
AREA_GROUP "core1_5" RANGE=SLICE_X34Y16:SLICE_X63Y34; # 30x19
AREA_GROUP "core1_5" RANGE=RAMB16_X2Y8:RAMB16_X2Y14;
AREA_GROUP "core1_6" RANGE=SLICE_X34Y35:SLICE_X63Y53; # 30x19
AREA_GROUP "core1_6" RANGE=RAMB16_X2Y18:RAMB16_X2Y24;
AREA_GROUP "core1_7" RANGE=SLICE_X34Y54:SLICE_X63Y72; # 30x19
AREA_GROUP "core1_7" RANGE=RAMB16_X2Y28:RAMB16_X2Y34;

// ------------------------------------------------------------
# Wrapper 2 - Top Right (unit #1)
// ------------------------------------------------------------
#
AREA_GROUP "wrapper2_in_r1" RANGE=SLICE_X94Y100:SLICE_X97Y103;
INST "pkt_comm/wrappers[2].wrapper/*in_r1*" AREA_GROUP="wrapper2_in_r1";
AREA_GROUP "wrapper2_in_r2" RANGE=SLICE_X94Y143:SLICE_X97Y155;
INST "pkt_comm/wrappers[2].wrapper/*in_r2*" AREA_GROUP="wrapper2_in_r2";
INST "pkt_comm/wrappers[2].wrapper/*out_r2*" AREA_GROUP="wrapper2_in_r2";
#
# right column
AREA_GROUP "core2_0" RANGE=SLICE_X98Y171:SLICE_X127Y189,SLICE_X98Y190:SLICE_X115Y191; # 30x19+
AREA_GROUP "core2_0" RANGE=RAMB16_X4Y86:RAMB16_X4Y94;
AREA_GROUP "core2_1" RANGE=SLICE_X98Y152:SLICE_X127Y170; # 30x19
AREA_GROUP "core2_1" RANGE=RAMB16_X4Y76:RAMB16_X4Y84;
AREA_GROUP "core2_2" RANGE=SLICE_X98Y133:SLICE_X127Y151;
AREA_GROUP "core2_2" RANGE=RAMB16_X4Y68:RAMB16_X4Y74;
AREA_GROUP "core2_3" RANGE=SLICE_X98Y114:SLICE_X127Y132;
AREA_GROUP "core2_3" RANGE=RAMB16_X4Y58:RAMB16_X4Y64;
AREA_GROUP "core2_4" RANGE=SLICE_X98Y95:SLICE_X127Y113;
AREA_GROUP "core2_4" RANGE=RAMB16_X4Y48:RAMB16_X4Y56;
#
# center-right column
AREA_GROUP "core2_5" RANGE=SLICE_X64Y160:SLICE_X93Y175,SLICE_X64Y176:SLICE_X81Y181; # 30x16+
AREA_GROUP "core2_5" RANGE=RAMB16_X3Y80:RAMB16_X3Y86;
AREA_GROUP "core2_6" RANGE=SLICE_X64Y141:SLICE_X93Y159; # 30x19
AREA_GROUP "core2_6" RANGE=RAMB16_X3Y70:RAMB16_X3Y78;
AREA_GROUP "core2_7" RANGE=SLICE_X64Y122:SLICE_X93Y140; # 30x19
AREA_GROUP "core2_7" RANGE=RAMB16_X3Y62:RAMB16_X3Y68;
AREA_GROUP "core2_8" RANGE=SLICE_X64Y103:SLICE_X93Y121; # 30x19
AREA_GROUP "core2_8" RANGE=RAMB16_X3Y52:RAMB16_X3Y60;

// ------------------------------------------------------------
# Wrapper 3 - Bottom Right (unit #1)
// ------------------------------------------------------------
#
AREA_GROUP "wrapper3_in_r1" RANGE=SLICE_X94Y73:SLICE_X97Y79;
INST "pkt_comm/wrappers[3].wrapper/*in_r1*" AREA_GROUP="wrapper3_in_r1";
AREA_GROUP "wrapper3_in_r2" RANGE=SLICE_X94Y37:SLICE_X97Y55;
INST "pkt_comm/wrappers[3].wrapper/*in_r2*" AREA_GROUP="wrapper3_in_r2";
INST "pkt_comm/wrappers[3].wrapper/*out_r2*" AREA_GROUP="wrapper3_in_r2";
#
# right column
AREA_GROUP "core3_0" RANGE=SLICE_X98Y2:SLICE_X127Y20; # 30x19
AREA_GROUP "core3_0" RANGE=RAMB16_X4Y2:RAMB16_X4Y10;
AREA_GROUP "core3_1" RANGE=SLICE_X98Y21:SLICE_X127Y39; # 30x19
AREA_GROUP "core3_1" RANGE=RAMB16_X4Y12:RAMB16_X4Y18;
AREA_GROUP "core3_2" RANGE=SLICE_X98Y40:SLICE_X127Y58; # 30x19
AREA_GROUP "core3_2" RANGE=RAMB16_X4Y20:RAMB16_X4Y26;
AREA_GROUP "core3_3" RANGE=SLICE_X98Y59:SLICE_X127Y77; # 30x19
AREA_GROUP "core3_3" RANGE=RAMB16_X4Y30:RAMB16_X4Y36;
#
# center-right column
AREA_GROUP "core3_4" RANGE=SLICE_X64Y16:SLICE_X93Y34; # 30x19
AREA_GROUP "core3_4" RANGE=RAMB16_X3Y8:RAMB16_X3Y14;
AREA_GROUP "core3_5" RANGE=SLICE_X64Y35:SLICE_X93Y53; # 30x19
AREA_GROUP "core3_5" RANGE=RAMB16_X3Y18:RAMB16_X3Y24;
AREA_GROUP "core3_6" RANGE=SLICE_X64Y54:SLICE_X93Y72; # 30x19
AREA_GROUP "core3_6" RANGE=RAMB16_X3Y26:RAMB16_X3Y34;


INST "pkt_comm/wrappers[0].wrapper/cores[0].core/*" AREA_GROUP="core0_0";
INST "pkt_comm/wrappers[0].wrapper/cores[1].core/*" AREA_GROUP="core0_1";
INST "pkt_comm/wrappers[0].wrapper/cores[2].core/*" AREA_GROUP="core0_2";
INST "pkt_comm/wrappers[0].wrapper/cores[3].core/*" AREA_GROUP="core0_3";
INST "pkt_comm/wrappers[0].wrapper/cores[4].core/*" AREA_GROUP="core0_4";
INST "pkt_comm/wrappers[0].wrapper/cores[5].core/*" AREA_GROUP="core0_5";
INST "pkt_comm/wrappers[0].wrapper/cores[6].core/*" AREA_GROUP="core0_6";
INST "pkt_comm/wrappers[0].wrapper/cores[7].core/*" AREA_GROUP="core0_7";

INST "pkt_comm/wrappers[1].wrapper/cores[0].core/*" AREA_GROUP="core1_0";
INST "pkt_comm/wrappers[1].wrapper/cores[1].core/*" AREA_GROUP="core1_1";
INST "pkt_comm/wrappers[1].wrapper/cores[2].core/*" AREA_GROUP="core1_2";
INST "pkt_comm/wrappers[1].wrapper/cores[3].core/*" AREA_GROUP="core1_3";
INST "pkt_comm/wrappers[1].wrapper/cores[4].core/*" AREA_GROUP="core1_4";
INST "pkt_comm/wrappers[1].wrapper/cores[5].core/*" AREA_GROUP="core1_5";
INST "pkt_comm/wrappers[1].wrapper/cores[6].core/*" AREA_GROUP="core1_6";
INST "pkt_comm/wrappers[1].wrapper/cores[7].core/*" AREA_GROUP="core1_7";

INST "pkt_comm/wrappers[2].wrapper/cores[0].core/*" AREA_GROUP="core2_0";
INST "pkt_comm/wrappers[2].wrapper/cores[1].core/*" AREA_GROUP="core2_1";
INST "pkt_comm/wrappers[2].wrapper/cores[2].core/*" AREA_GROUP="core2_2";
INST "pkt_comm/wrappers[2].wrapper/cores[3].core/*" AREA_GROUP="core2_3";
INST "pkt_comm/wrappers[2].wrapper/cores[4].core/*" AREA_GROUP="core2_4";
INST "pkt_comm/wrappers[2].wrapper/cores[5].core/*" AREA_GROUP="core2_5";
INST "pkt_comm/wrappers[2].wrapper/cores[6].core/*" AREA_GROUP="core2_6";
INST "pkt_comm/wrappers[2].wrapper/cores[7].core/*" AREA_GROUP="core2_7";
INST "pkt_comm/wrappers[2].wrapper/cores[8].core/*" AREA_GROUP="core2_8";

INST "pkt_comm/wrappers[3].wrapper/cores[0].core/*" AREA_GROUP="core3_0";
INST "pkt_comm/wrappers[3].wrapper/cores[1].core/*" AREA_GROUP="core3_1";
INST "pkt_comm/wrappers[3].wrapper/cores[2].core/*" AREA_GROUP="core3_2";
INST "pkt_comm/wrappers[3].wrapper/cores[3].core/*" AREA_GROUP="core3_3";
INST "pkt_comm/wrappers[3].wrapper/cores[4].core/*" AREA_GROUP="core3_4";
INST "pkt_comm/wrappers[3].wrapper/cores[5].core/*" AREA_GROUP="core3_5";
INST "pkt_comm/wrappers[3].wrapper/cores[6].core/*" AREA_GROUP="core3_6";


NET "pkt_comm/cmp_config/salt_out*" TIG;
NET "pkt_comm/cmp_config/read_addr_start*" TIG;
NET "pkt_comm/cmp_config/addr_diff_start*" TIG;
NET "pkt_comm/cmp_config/prev_num_hashes*" TIG;

NET "pkt_comm/cmp_config_distrib/global_salt_r*" TIG;
NET "pkt_comm/global_salt*" TIG;
PIN "pkt_comm/cmp_config_distrib/global_wires_salt/global_wires[*].BUFG_0.O" CLOCK_DEDICATED_ROUTE = FALSE;

PIN "clocks/cmt3/BUFGCE_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "clocks/cmt2/BUFGCE_inst0.O" CLOCK_DEDICATED_ROUTE = FALSE;

NET "pkt_comm/wrappers[*].wrapper/cores[*].core/salt_r*" TIG;
NET "pkt_comm/wrappers[*].wrapper/cores[*].core/read_addr_start*" TIG;
NET "pkt_comm/wrappers[*].wrapper/cores[*].core/addr_diff_start*" TIG;
NET "pkt_comm/wrappers[*].wrapper/cores[*].core/cmp_batch_num*" TIG;
NET "pkt_comm/wrappers[*].wrapper/cores[*].core/cmp_pkt_num*" TIG;
