#
# This software is Copyright (c) 2016,2019 Denis Burykin
# [denis_burykin yahoo com], [denis-burykin2014 yandex ru]
# and it is hereby released to the general public under the following terms:
# Redistribution and use in source and binary forms, with or without
# modification, are permitted.
#
# ****************************
#
# cmt2 - driven by IFCLK_IN
# cmt2.v
# DCM_PS + (optional)DCM + (optional)PLL
#
# ****************************
#
#INST "clocks/cmt2/BUFIO2_inst" LOC=BUFIO2_X3Y13;
INST "clocks/cmt2/DCM_0" LOC=DCM_X0Y4;
NET "IFCLK" TNM_NET = "IFCLK";
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20.833 ns HIGH 50%;

# CLK2X
NET "clocks/cmt2/dcm0_clk2x" TNM_NET = "cmt2_dcm0_clk2x";
#TIMESPEC "TS_cmt2_dcm0_clk2x" = PERIOD "cmt2_dcm0_clk2x" 10.416 ns HIGH 50%;
TIMESPEC "TS_PKT_COMM_CLK" = PERIOD "cmt2_dcm0_clk2x" 10.416 ns HIGH 50%; # name for Timing Constraints Report

# CLK2
#INST "clocks/cmt2/DCM_CLKGEN_0" LOC=DCM_X0Y5;
#NET "clocks/cmt2/dcm0_clk90" TNM_NET = "cmt2_dcm0_clk90";
#TIMESPEC "TS_cmt2_dcm0_clk90" = PERIOD "cmt2_dcm0_clk90" 20.833 ns HIGH 50%;
#TIMESPEC "TS_WORD_GEN_CLK" = PERIOD "cmt2_dcm0_clk90" 20.833 ns HIGH 50%;

# PLL_CLK
#INST "clocks/cmt2/PLL_0" LOC=PLL_ADV_X0Y2;
#NET "clocks/cmt2/dcm0_clkdv" TNM_NET = "cmt2_dcm0_clkdv";
#TIMESPEC "TS_cmt2_dcm0_clkdv" = PERIOD "cmt2_dcm0_clkdv" 41.666 ns HIGH 50%;
#TIMESPEC "TS_PKT_COMM_CLK" = PERIOD "cmt2_dcm0_clkdv" 41.666 ns HIGH 50%;


# ****************************
#
# Programmable clock #0
# cmt_prog.v
# DCM_CLKGEN + PLL
#
# ****************************
#
INST "clocks/cmt3/DCM_CLKGEN_0" LOC=DCM_X0Y7;
INST "clocks/cmt3/PLL_0" LOC=PLL_ADV_X0Y3;

NET "clocks/cmt3/pll0_clkout0" TNM_NET = "CORE_CLK";
//TIMESPEC "TS_CORE_CLK" = PERIOD "CORE_CLK" 4.347 ns HIGH 50%; // 230
//TIMESPEC "TS_CORE_CLK" = PERIOD "CORE_CLK" 4.444 ns HIGH 50%; // 225
//TIMESPEC "TS_CORE_CLK" = PERIOD "CORE_CLK" 4.504 ns HIGH 50%; // 222
TIMESPEC "TS_CORE_CLK" = PERIOD "CORE_CLK" 4.545 ns HIGH 50%; // 220
//TIMESPEC "TS_CORE_CLK" = PERIOD "CORE_CLK" 5.000 ns HIGH 50%; // 200


# ****************************
#
# Programmable clock #1
# cmt_prog.v
#
# ****************************
#
INST "clocks/cmt4/DCM_CLKGEN_0" LOC=DCM_X0Y9;
INST "clocks/cmt4/PLL_0" LOC=PLL_ADV_X0Y4;

NET "clocks/cmt4/pll0_clkout0" TNM_NET = "CMP_CLK";
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 4.761 ns HIGH 50%; // 210
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 5.000 ns HIGH 50%; // 200
TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 5.128 ns HIGH 50%; // 195
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 5.263 ns HIGH 50%; // 190
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 5.405 ns HIGH 50%; // 185
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 5.555 ns HIGH 50%; // 180
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 6.060 ns HIGH 50%; // 165
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 6.172 ns HIGH 50%; // 162
//TIMESPEC "TS_CMP_CLK" = PERIOD "CMP_CLK" 6.250 ns HIGH 50%; // 160

