Using as: Machine Dependencies

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# 9. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where `as` runs. Floating point representations vary as well, and `as` often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of `as` support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

> 9.1 Alpha Dependent Features |  |
> 9.2 ARC Dependent Features |  |
> 9.3 ARM Dependent Features |  |
> 9.4 AVR Dependent Features |  |
> 9.5 Blackfin Dependent Features |  |
> 9.6 CR16 Dependent Features |  |
> 9.7 CRIS Dependent Features |  |
> 9.8 D10V Dependent Features |  |
> 9.9 D30V Dependent Features |  |
> 9.10 Epiphany Dependent Features |  | EPIPHANY Dependent Features
> 9.11 H8/300 Dependent Features |  | Renesas H8/300 Dependent Features
> 9.12 HPPA Dependent Features |  |
> 9.13 ESA/390 Dependent Features |  | IBM ESA/390 Dependent Features
> 9.14 80386 Dependent Features |  | Intel 80386 and AMD x86-64 Dependent Features
> 9.15 Intel i860 Dependent Features |  | Intel 80860 Dependent Features
> 9.16 Intel 80960 Dependent Features |  |
> 9.17 IA-64 Dependent Features |  | Intel IA-64 Dependent Features
> 9.18 IP2K Dependent Features |  |
> 9.19 LM32 Dependent Features |  |
> 9.20 M32C Dependent Features |  |
> 9.21 M32R Dependent Features |  |
> 9.22 M680x0 Dependent Features |  |
> 9.23 M68HC11 and M68HC12 Dependent Features |  | M68HC11 and 68HC12 Dependent Features
> 9.24 MicroBlaze Dependent Features |  | MICROBLAZE Dependent Features
> 9.25 MIPS Dependent Features |  |
> 9.26 MMIX Dependent Features |  |
> 9.27 MSP 430 Dependent Features |  |
> 9.28 NS32K Dependent Features |  |
> 9.36 Renesas / SuperH SH Dependent Features |  |
> 9.37 SuperH SH64 Dependent Features |  |
> 9.29 PDP-11 Dependent Features |  |
> 9.30 picoJava Dependent Features |  |
> 9.31 PowerPC Dependent Features |  |
> 9.32 RL78 Dependent Features |  |
> 9.33 RX Dependent Features |  |
> 9.34 IBM S/390 Dependent Features |  |
> 9.35 SCORE Dependent Features |  |
> 9.38 SPARC Dependent Features |  |
> 9.39 TIC54X Dependent Features |  | TI TMS320C54x Dependent Features
> 9.40 TIC6X Dependent Features |  | TI TMS320C6x Dependent Features
> 9.41 TILE-Gx Dependent Features |  | Tilera TILE-Gx Dependent Features
> 9.42 TILEPro Dependent Features |  | Tilera TILEPro Dependent Features
> 9.46 v850 Dependent Features |  | V850 Dependent Features
> 9.47 XStormy16 Dependent Features |  |
> 9.48 Xtensa Dependent Features |  |
> 9.43 Z80 Dependent Features |  |
> 9.44 Z8000 Dependent Features |  |
> 9.45 VAX Dependent Features |  |

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## 9.1 Alpha Dependent Features

> 9.1.1 Notes |  |
> 9.1.2 Options |  |
> 9.1.3 Syntax |  |
> 9.1.4 Floating Point |  |
> 9.1.5 Alpha Assembler Directives |  | Alpha Machine Directives
> 9.1.6 Opcodes |  |

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### 9.1.1 Notes

The documentation here is primarily for the ELF object format. `as` also supports the ECOFF and EVAX formats, but features specific to these formats are not yet documented.

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### 9.1.2 Options

`-mcpu`
  This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the `.arch` directive.

  The following processor names are recognized: `21064`, `21064a`, `21066`, `21068`, `21164`, `21164a`, `21164pc`, `21264`, `21264a`, `21264b`, `ev4`, `ev5`, `lca45`, `ev5`, `ev56`, `pca56`, `ev6`, `ev67`, `ev68`. The special name `all` may be used to allow the assembler to accept instructions valid for any Alpha processor.

  In order to support existing practice in OSF/1 with respect to `.arch`, and existing practice within `MILO` (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. `ev4`) do not.

`-mdebug`
`-no-mdebug`
  Enables or disables the generation of `.mdebug` encapsulation for stabs directives and procedure descriptors. The default is to automatically enable `.mdebug` when the first stabs directive is seen.

`-relax`
  This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.

`-replace`
`-noreplace`
  Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and `-replace` is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.

`-g`
  This option is used when the compiler generates debug information. When `gcc` is using `mips-tfile` to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.

`-Gsize`
  A local common symbol larger than size is placed in `.bss`, while smaller symbols are placed in `.sbss`.

`-F`
`-32addr`
  These options are ignored for backward compatibility.

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### 9.1.3 Syntax

The assembler syntax closely follow the Alpha Reference Manual; assembler directives and general syntax closely follow the OSF/1 and OpenVMS syntax, with a few differences for ELF.

> 9.1.3.1 Special Characters |  |
> 9.1.3.2 Register Names |  |
> 9.1.3.3 Relocations |  |

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#### 9.1.3.1 Special Characters

``#'` is the line comment character. Note that if ``#'` is the first character on a line then it can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

``;'` can be used instead of a newline to separate statements.

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#### 9.1.3.2 Register Names

The 32 integer registers are referred to as ``$n'` or ``$rn'`. In addition, registers 15, 28, 29, and 30 may be referred to by the symbols ``$fp'`, ``$at'`, ``$gp'`, and ``$sp'` respectively.

The 32 floating-point registers are referred to as ``$fn'`.

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#### 9.1.3.3 Relocations

Some of these relocations are available for ECOFF, but mostly only for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions.

The format is ``!tag'` or ``!tag!number'` where tag is the name of the relocation. In some cases number is used to relate specific instructions.

The relocation is placed at the end of the instruction like so:

    ldah  $0,a($29)    !gprelhigh
    lda   $0,a($0)     !gprellow
    ldq   $1,b($29)    !literal!100
    ldl   $2,0($1)     !lituse_base!100

`!literal`
`!literal!N`
  Used with an `ldq` instruction to load the address of a symbol from the GOT.

  A sequence number N is optional, and if present is used to pair `lituse` relocations with this `literal` relocation. The `lituse` relocations are used by the linker to optimize the code based on the final location of the symbol.

  Note that these optimizations are dependent on the data flow of the program. Therefore, if any `lituse` is paired with a `literal` relocation, then all uses of the register set by the `literal` instruction must also be marked with `lituse` relocations. This is because the original `literal` instruction may be deleted or transformed into another instruction.

  Also note that there may be a one-to-many relationship between `literal` and `lituse`, but not a many-to-one. That is, if there are two code paths that load up the same address and feed the value to a single use, then the use may not use a `lituse` relocation.

`!lituse_base!N`
  Used with any memory format instruction (e.g. `ldl`) to indicate that the literal is used for an address load. The offset field of the instruction must be zero. During relaxation, the code may be altered to use a gp-relative load.

`!lituse_jsr!N`
  Used with a register branch format instruction (e.g. `jsr`) to indicate that the literal is used for a call. During relaxation, the code may be altered to use a direct branch (e.g. `bsr`).

`!lituse_jsrdirect!N`
  Similar to `lituse_jsr`, but also that this call cannot be vectored through a PLT entry. This is useful for functions with special calling conventions which do not allow the normal call-clobbered registers to be clobbered.

`!lituse_bytoff!N`
  Used with a byte mask instruction (e.g. `extbl`) to indicate that only the low 3 bits of the address are relevant. During relaxation, the code may be altered to use an immediate instead of a register shift.

`!lituse_addr!N`
  Used with any other instruction to indicate that the original address is in fact used, and the original `ldq` instruction may not be altered or deleted. This is useful in conjunction with `lituse_jsr` to test whether a weak symbol is defined.

      ldq  $27,foo($29)   !literal!1
      beq  $27,is_undef   !lituse_addr!1
      jsr  $26,($27),foo  !lituse_jsr!1

`!lituse_tlsgd!N`
  Used with a register branch format instruction to indicate that the literal is the call to `__tls_get_addr` used to compute the address of the thread-local storage variable whose descriptor was loaded with `!tlsgd!N`.

`!lituse_tlsldm!N`
  Used with a register branch format instruction to indicate that the literal is the call to `__tls_get_addr` used to compute the address of the base of the thread-local storage block for the current module. The descriptor for the module must have been loaded with `!tlsldm!N`.

`!gpdisp!N`
  Used with `ldah` and `lda` to load the GP from the current address, a-la the `ldgp` macro. The source register for the `ldah` instruction must contain the address of the `ldah` instruction. There must be exactly one `lda` instruction paired with the `ldah` instruction, though it may appear anywhere in the instruction stream. The immediate operands must be zero.

      bsr  $26,foo
      ldah $29,0($26)     !gpdisp!1
      lda  $29,0($29)     !gpdisp!1

`!gprelhigh`
  Used with an `ldah` instruction to add the high 16 bits of a 32-bit displacement from the GP.

`!gprellow`
  Used with any memory format instruction to add the low 16 bits of a 32-bit displacement from the GP.

`!gprel`
  Used with any memory format instruction to add a 16-bit displacement from the GP.

`!samegp`
  Used with any branch format instruction to skip the GP load at the target address. The referenced symbol must have the same GP as the source object file, and it must be declared to either not use `$27` or perform a standard GP load in the first two instructions via the `.prologue` directive.

`!tlsgd`
`!tlsgd!N`
  Used with an `lda` instruction to load the address of a TLS descriptor for a symbol in the GOT.

  The sequence number N is optional, and if present it used to pair the descriptor load with both the `literal` loading the address of the `__tls_get_addr` function and the `lituse_tlsgd` marking the call to that function.

  For proper relaxation, both the `tlsgd`, `literal` and `lituse` relocations must be in the same extended basic block. That is, the relocation with the lowest address must be executed first at runtime.

`!tlsldm`
`!tlsldm!N`
  Used with an `lda` instruction to load the address of a TLS descriptor for the current module in the GOT.

  Similar in other respects to `tlsgd`.

`!gotdtprel`
  Used with an `ldq` instruction to load the offset of the TLS symbol within its module's thread-local storage block. Also known as the dynamic thread pointer offset or dtp-relative offset.

`!dtprelhi`
`!dtprello`
`!dtprel`
  Like `gprel` relocations except they compute dtp-relative offsets.

`!gottprel`
  Used with an `ldq` instruction to load the offset of the TLS symbol from the thread pointer. Also known as the tp-relative offset.

`!tprelhi`
`!tprello`
`!tprel`
  Like `gprel` relocations except they compute tp-relative offsets.

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### 9.1.4 Floating Point

The Alpha family uses both IEEE and VAX floating-point numbers.

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### 9.1.5 Alpha Assembler Directives

`as` for the Alpha supports many additional directives for compatibility with the native assembler. This section describes them only briefly.

These are the additional directives in `as` for the Alpha:

`.arch cpu`
  Specifies the target processor. This is equivalent to the ``-mcpu'` command-line option. See section Options, for a list of values for cpu.

`.ent function[, n]`
  Mark the beginning of function. An optional number may follow for compatibility with the OSF/1 assembler, but is ignored. When generating `.mdebug` information, this will create a procedure descriptor for the function. In ELF, it will mark the symbol as a function a-la the generic `.type` directive.

`.end function`
  Mark the end of function. In ELF, it will set the size of the symbol a-la the generic `.size` directive.

`.mask mask, offset`
  Indicate which of the integer registers are saved in the current function's stack frame. mask is interpreted a bit mask in which bit n set indicates that register n is saved. The registers are saved in a block located offset bytes from the canonical frame address (CFA) which is the value of the stack pointer on entry to the function. The registers are saved sequentially, except that the return address register (normally `$26`) is saved first.

  This and the other directives that describe the stack frame are currently only used when generating `.mdebug` information. They may in the future be used to generate DWARF2 `.debug_frame` unwind information for hand written assembly.

`.fmask mask, offset`
  Indicate which of the floating-point registers are saved in the current stack frame. The mask and offset parameters are interpreted as with `.mask`.

`.frame framereg, frameoffset, retreg[, argoffset]`
  Describes the shape of the stack frame. The frame pointer in use is framereg; normally this is either `$fp` or `$sp`. The frame pointer is frameoffset bytes below the CFA. The return address is initially located in retreg until it is saved as indicated in `.mask`. For compatibility with OSF/1 an optional argoffset parameter is accepted and ignored. It is believed to indicate the offset from the CFA to the saved argument registers.

`.prologue n`
  Indicate that the stack frame is set up and all registers have been spilled. The argument n indicates whether and how the function uses the incoming procedure vector (the address of the called function) in `$27`. 0 indicates that `$27` is not used; 1 indicates that the first two instructions of the function use `$27` to perform a load of the GP register; 2 indicates that `$27` is used in some non-standard way and so the linker cannot elide the load of the procedure vector during relaxation.

`.usepv function, which`
  Used to indicate the use of the `$27` register, similar to `.prologue`, but without the other semantics of needing to be inside an open `.ent`/`.end` block.

  The which argument should be either `no`, indicating that `$27` is not used, or `std`, indicating that the first two instructions of the function perform a GP load.

  One might use this directive instead of `.prologue` if you are also using dwarf2 CFI directives.

`.gprel32 expression`
  Computes the difference between the address in expression and the GP for the current object file, and stores it in 4 bytes. In addition to being smaller than a full 8 byte address, this also does not require a dynamic relocation when used in a shared library.

`.t_floating expression`
  Stores expression as an IEEE double precision value.

`.s_floating expression`
  Stores expression as an IEEE single precision value.

`.f_floating expression`
  Stores expression as a VAX F format value.

`.g_floating expression`
  Stores expression as a VAX G format value.

`.d_floating expression`
  Stores expression as a VAX D format value.

`.set feature`
  Enables or disables various assembler features. Using the positive name of the feature enables while using ``nofeature'` disables.

  `at`
    Indicates that macro expansions may clobber the assembler temporary (`$at` or `$28`) register. Some macros may not be expanded without this and will generate an error message if `noat` is in effect. When `at` is in effect, a warning will be generated if `$at` is used by the programmer.

  `macro`
    Enables the expansion of macro instructions. Note that variants of real instructions, such as `br label` vs `br $31,label` are considered alternate forms and not macros.

  `move`
  `reorder`
  `volatile`
    These control whether and how the assembler may re-order instructions. Accepted for compatibility with the OSF/1 assembler, but `as` does not do instruction scheduling, so these features are ignored.

The following directives are recognized for compatibility with the OSF/1 assembler but are ignored.

    .proc           .aproc
    .reguse         .livereg
    .option         .aent
    .ugen           .eflag
    .alias          .noalias

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### 9.1.6 Opcodes

For detailed information on the Alpha machine instruction set, see the Alpha Architecture Handbook.

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## 9.2 ARC Dependent Features

> 9.2.1 Options |  |
> 9.2.2 Syntax |  |
> 9.2.3 Floating Point |  |
> 9.2.4 ARC Machine Directives |  |
> 9.2.5 Opcodes |  |

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### 9.2.1 Options

`-marc[5|6|7|8]`
  This option selects the core processor variant. Using `-marc` is the same as `-marc6`, which is also the default.

  `arc5`
    Base instruction set.

  `arc6`
    Jump-and-link (jl) instruction. No requirement of an instruction between setting flags and conditional jump. For example:

          mov.f r0,r1
          beq   foo

  `arc7`
    Break (brk) and sleep (sleep) instructions.

  `arc8`
    Software interrupt (swi) instruction.

  Note: the `.option` directive can to be used to select a core variant from within assembly code.

`-EB`
  This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

`-EL`
  This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default.

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### 9.2.2 Syntax

> 9.2.2.1 Special Characters |  |
> 9.2.2.2 Register Names |  |

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#### 9.2.2.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line. Note that if a line starts with a ``#'` character then it can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ARC assembler does not support a line separator character.

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#### 9.2.2.2 Register Names

*TODO*

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### 9.2.3 Floating Point

The ARC core does not currently have hardware floating point support. Software floating point support is provided by `GCC` and uses IEEE floating-point numbers.

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### 9.2.4 ARC Machine Directives

The ARC version of `as` supports the following additional machine directives:

`.2byte expressions`
  *TODO*

`.3byte expressions`
  *TODO*

`.4byte expressions`
  *TODO*

`.extAuxRegister name,address,mode`
  The ARCtangent A4 has extensible auxiliary register space. The auxiliary registers can be defined in the assembler source code by using this directive. The first parameter is the name of the new auxiallry register. The second parameter is the address of the register in the auxiliary register memory map for the variant of the ARC. The third parameter specifies the mode in which the register can be operated is and it can be one of:

  `r (readonly)`
  `w (write only)`
  `r|w (read or write)`

  For example:

        .extAuxRegister mulhi,0x12,w

  This specifies an extension auxiliary register called mulhi which is at address 0x12 in the memory space and which is only writable.

`.extCondCode suffix,value`
  The condition codes on the ARCtangent A4 are extensible and can be specified by means of this assembler directive. They are specified by the suffix and the value for the condition code. They can be used to specify extra condition codes with any values. For example:

        .extCondCode is_busy,0x14

         add.is_busy  r1,r2,r3
         bis_busy     _main

`.extCoreRegister name,regnum,mode,shortcut`
  Specifies an extension core register name for the application. This allows a register name with a valid regnum between 0 and 60, with the following as valid values for mode

  ``r (readonly)'`
  ``w (write only)'`
  ``r|w (read or write)'`

  The other parameter gives a description of the register having a shortcut in the pipeline. The valid values are:

  `can_shortcut`
  `cannot_shortcut`

  For example:

        .extCoreRegister mlo,57,r,can_shortcut

  This defines an extension core register mlo with the value 57 which can shortcut the pipeline.

`.extInstruction name,opcode,subopcode,suffixclass,syntaxclass`
  The ARCtangent A4 allows the user to specify extension instructions. The extension instructions are not macros. The assembler creates encodings for use of these instructions according to the specification by the user. The parameters are:

  - name Name of the extension instruction

  - opcode Opcode to be used. (Bits 27:31 in the encoding). Valid values 0x10-0x1f or 0x03

  - subopcode Subopcode to be used. Valid values are from 0x09-0x3f. However the correct value also depends on syntaxclass

  - suffixclass Determines the kinds of suffixes to be allowed. Valid values are `SUFFIX_NONE`, `SUFFIX_COND`, `SUFFIX_FLAG` which indicates the absence or presence of conditional suffixes and flag setting by the extension instruction. It is also possible to specify that an instruction sets the flags and is conditional by using `SUFFIX_CODE` | `SUFFIX_FLAG`.

  - syntaxclass Determines the syntax class for the instruction. It can have the following values:

    ``SYNTAX_2OP`:`
      2 Operand Instruction
    ``SYNTAX_3OP`:`
      3 Operand Instruction

    In addition there could be modifiers for the syntax class as described below:

    Syntax Class Modifiers are:
    - `OP1_MUST_BE_IMM`: Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with SYNTAX_3OP as given in the example below. This could usually be used to set the flags using specific instructions and not retain results.

    - `OP1_IMM_IMPLIED`: Modifies syntax class SYNTAX_20P, it specifies that there is an implied immediate destination operand which does not appear in the syntax. For example, if the source code contains an instruction like:

          inst r1,r2

      it really means that the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it with SYNTAX_20P.

  For example, defining 64-bit multiplier with immediate operands:

      .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
                      SYNTAX_3OP|OP1_MUST_BE_IMM

  The above specifies an extension instruction called mp64 which has 3 operands, sets the flags, can be used with a condition code, for which the first operand is an immediate. (Equivalent to discarding the result of the operation).

       .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED

  This describes a 2 operand instruction with an implicit first immediate operand. The result of this operation would be discarded.

`.half expressions`
  *TODO*

`.long expressions`
  *TODO*

`.option arc|arc5|arc6|arc7|arc8`
  The `.option` directive must be followed by the desired core version. Again `arc` is an alias for `arc6`.

  Note: the `.option` directive overrides the command line option `-marc`; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6).

`.short expressions`
  *TODO*

`.word expressions`
  *TODO*

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### 9.2.5 Opcodes

For information on the ARC instruction set, see ARC Programmers Reference Manual, ARC International (www.arc.com)

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## 9.3 ARM Dependent Features

> 9.3.1 Options |  |
> 9.3.2 Syntax |  |
> 9.3.3 Floating Point |  |
> 9.3.4 ARM Machine Directives |  |
> 9.3.5 Opcodes |  |
> 9.3.6 Mapping Symbols |  |
> 9.3.7 Unwinding |  |

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### 9.3.1 Options

`-mcpu=processor[+extension...]`
  This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: `arm1`, `arm2`, `arm250`, `arm3`, `arm6`, `arm60`, `arm600`, `arm610`, `arm620`, `arm7`, `arm7m`, `arm7d`, `arm7dm`, `arm7di`, `arm7dmi`, `arm70`, `arm700`, `arm700i`, `arm710`, `arm710t`, `arm720`, `arm720t`, `arm740t`, `arm710c`, `arm7100`, `arm7500`, `arm7500fe`, `arm7t`, `arm7tdmi`, `arm7tdmi-s`, `arm8`, `arm810`, `strongarm`, `strongarm1`, `strongarm110`, `strongarm1100`, `strongarm1110`, `arm9`, `arm920`, `arm920t`, `arm922t`, `arm940t`, `arm9tdmi`, `fa526` (Faraday FA526 processor), `fa626` (Faraday FA626 processor), `arm9e`, `arm926e`, `arm926ej-s`, `arm946e-r0`, `arm946e`, `arm946e-s`, `arm966e-r0`, `arm966e`, `arm966e-s`, `arm968e-s`, `arm10t`, `arm10tdmi`, `arm10e`, `arm1020`, `arm1020t`, `arm1020e`, `arm1022e`, `arm1026ej-s`, `fa606te` (Faraday FA606TE processor), `fa616te` (Faraday FA616TE processor), `fa626te` (Faraday FA626TE processor), `fmp626` (Faraday FMP626 processor), `fa726te` (Faraday FA726TE processor), `arm1136j-s`, `arm1136jf-s`, `arm1156t2-s`, `arm1156t2f-s`, `arm1176jz-s`, `arm1176jzf-s`, `mpcore`, `mpcorenovfp`, `cortex-a5`, `cortex-a7`, `cortex-a8`, `cortex-a9`, `cortex-a15`, `cortex-r4`, `cortex-r4f`, `cortex-r5`, `cortex-r7`, `cortex-m4`, `cortex-m3`, `cortex-m1`, `cortex-m0`, `cortex-m0plus`, `ep9312` (ARM920 with Cirrus Maverick coprocessor), `i80200` (Intel XScale processor) `iwmmxt` (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and `xscale`. The special name `all` may be used to allow the assembler to accept instructions valid for any ARM processor.

  In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, `-mcpu=arm920+maverick` is equivalent to specifying `-mcpu=ep9312`.

  Multiple extensions may be specified, separated by a `+`. The extensions should be specified in ascending alphabetical order.

  Some extensions may be restricted to particular architectures; this is documented in the list of extensions below.

  Extension mnemonics may also be removed from those the assembler accepts. This is done be prepending `no` to the option that adds the extension. Extensions that are removed should be listed after all extensions which have been added, again in ascending alphabetical order. For example, `-mcpu=ep9312+nomaverick` is equivalent to specifying `-mcpu=arm920`.

  The following extensions are currently supported: `crypto` (Cryptography Extensions for v8-A architecture, implies `fp+simd`), `fp` (Floating Point Extensions for v8-A architecture), `idiv` (Integer Divide Extensions for v7-A and v7-R architectures), `iwmmxt`, `iwmmxt2`, `maverick`, `mp` (Multiprocessing Extensions for v7-A and v7-R architectures), `os` (Operating System for v6M architecture), `sec` (Security Extensions for v6K and v7-A architectures), `simd` (Advanced SIMD Extensions for v8-A architecture, implies `fp`), `virt` (Virtualization Extensions for v7-A architecture, implies `idiv`), and `xscale`.

`-march=architecture[+extension...]`
  This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: `armv1`, `armv2`, `armv2a`, `armv2s`, `armv3`, `armv3m`, `armv4`, `armv4xm`, `armv4t`, `armv4txm`, `armv5`, `armv5t`, `armv5txm`, `armv5te`, `armv5texp`, `armv6`, `armv6j`, `armv6k`, `armv6z`, `armv6zk`, `armv6-m`, `armv6s-m`, `armv7`, `armv7-a`, `armv7ve`, `armv7-r`, `armv7-m`, `armv7e-m`, `armv8-a`, `iwmmxt` and `xscale`. If both `-mcpu` and `-march` are specified, the assembler will use the setting for `-mcpu`.

  The architecture option can be extended with the same instruction set extension options as the `-mcpu` option.

`-mfpu=floating-point-format`

  This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: `softfpa`, `fpe`, `fpe2`, `fpe3`, `fpa`, `fpa10`, `fpa11`, `arm7500fe`, `softvfp`, `softvfp+vfp`, `vfp`, `vfp10`, `vfp10-r0`, `vfp9`, `vfpxd`, `vfpv2`, `vfpv3`, `vfpv3-fp16`, `vfpv3-d16`, `vfpv3-d16-fp16`, `vfpv3xd`, `vfpv3xd-d16`, `vfpv4`, `vfpv4-d16`, `fpv4-sp-d16`, `fp-armv8`, `arm1020t`, `arm1020e`, `arm1136jf-s`, `maverick`, `neon`, `neon-vfpv4`, `neon-fp-armv8`, and `crypto-neon-fp-armv8`.

  In addition to determining which instructions are assembled, this option also affects the way in which the `.double` assembler directive behaves when assembling little-endian code.

  The default is dependent on the processor selected. For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.

`-mthumb`
  This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file starts with a `.code 16` directive.

`-mthumb-interwork`
  This option specifies that the output generated by the assembler should be marked as supporting interworking.

`-mimplicit-it=never`
`-mimplicit-it=always`
`-mimplicit-it=arm`
`-mimplicit-it=thumb`
  The `-mimplicit-it` option controls the behavior of the assembler when conditional instructions are not enclosed in IT blocks. There are four possible behaviors. If `never` is specified, such constructs cause a warning in ARM code and an error in Thumb-2 code. If `always` is specified, such constructs are accepted in both ARM and Thumb-2 code, where the IT instruction is added implicitly. If `arm` is specified, such constructs are accepted in ARM code and cause an error in Thumb-2 code. If `thumb` is specified, such constructs cause a warning in ARM code and are accepted in Thumb-2 code. If you omit this option, the behavior is equivalent to `-mimplicit-it=arm`.

`-mapcs-26`
`-mapcs-32`
  These options specify that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

`-matpcs`
  This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can use this to determine the ABI being used by.

`-mapcs-float`
  This indicates the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.

`-mapcs-reentrant`
  This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

`-mfloat-abi=abi`
  This option specifies that the output generated by the assembler should be marked as using specified floating point ABI. The following values are recognized: `soft`, `softfp` and `hard`.

`-meabi=ver`
  This option specifies which EABI version the produced object files should conform to. The following values are recognized: `gnu`, `4` and `5`.

`-EB`
  This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

`-EL`
  This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

`-k`
  This option specifies that the output of the assembler should be marked as position-independent code (PIC).

`--fix-v4bx`
  Allow `BX` instructions in ARMv4 code. This is intended for use with the linker option of the same name.

`-mwarn-deprecated`
`-mno-warn-deprecated`
  Enable or disable warnings about using deprecated options or features. The default is to warn.

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### 9.3.2 Syntax

> 9.3.2.1 Instruction Set Syntax |  | Instruction Set
> 9.3.2.2 Special Characters |  |
> 9.3.2.3 Register Names |  |
> 9.3.2.4 ARM relocation generation |  | Relocations
> 9.3.2.5 NEON Alignment Specifiers |  |

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#### 9.3.2.1 Instruction Set Syntax

Two slightly different syntaxes are support for ARM and THUMB instructions. The default, `divided`, uses the old style where ARM and THUMB instructions had their own, separate syntaxes. The new, `unified` syntax, which can be selected via the `.syntax` directive, and has the following main features:

- Immediate operands do not require a `#` prefix.

- The `IT` instruction may appear, and if it does it is validated against subsequent conditional affixes. In ARM mode it does not generate machine code, in THUMB mode it does.

- For ARM instructions the conditional affixes always appear at the end of the instruction. For THUMB instructions conditional affixes can be used, but only inside the scope of an `IT` instruction.

- All of the instructions new to the V6T2 architecture (and later) are available. (Only a few such instructions can be written in the `divided` syntax).

- The `.N` and `.W` suffixes are recognized and honored.

- All instructions set the flags if and only if they have an `s` affix.

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#### 9.3.2.2 Special Characters

The presence of a ``@'` anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used instead of a newline to separate statements.

Either ``#'` or ``$'` can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

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#### 9.3.2.3 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

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#### 9.3.2.4 ARM relocation generation

Specific data relocations can be generated by putting the relocation name in parentheses after the symbol name. For example:

            .word foo(TARGET1)

This will generate an ``R_ARM_TARGET1'` relocation against the symbol foo. The following relocations are supported: `GOT`, `GOTOFF`, `TARGET1`, `TARGET2`, `SBREL`, `TLSGD`, `TLSLDM`, `TLSLDO`, `TLSDESC`, `TLSCALL`, `GOTTPOFF`, `GOT_PREL` and `TPOFF`.

For compatibility with older toolchains the assembler also accepts `(PLT)` after branch targets. On legacy targets this will generate the deprecated ``R_ARM_PLT32'` relocation. On EABI targets it will encode either the ``R_ARM_CALL'` or ``R_ARM_JUMP24'` relocation, as appropriate.

Relocations for ``MOVW'` and ``MOVT'` instructions can be generated by prefixing the value with ``#:lower16:'` and ``#:upper16'` respectively. For example to load the 32-bit address of foo into r0:

            MOVW r0, #:lower16:foo
            MOVT r0, #:upper16:foo

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#### 9.3.2.5 NEON Alignment Specifiers

Some NEON load/store instructions allow an optional address alignment qualifier. The ARM documentation specifies that this is indicated by ``@ align'`. However GAS already interprets the ``@'` character as a "line comment" start, so ``: align'` is used instead. For example:

            vld1.8 {q0}, [r0, :128]

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### 9.3.3 Floating Point

The ARM family uses IEEE floating-point numbers.

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### 9.3.4 ARM Machine Directives

`.2byte expression [, expression]*`
`.4byte expression [, expression]*`
`.8byte expression [, expression]*`
  These directives write 2, 4 or 8 byte values to the output section.

`.align expression [, expression]`
  This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatibility with ARM's own assembler.

`.arch name`
  Select the target architecture. Valid values for name are the same as for the ``-march'` commandline option.

  Specifying `.arch` clears any previously selected architecture extensions.

`.arch_extension name`
  Add or remove an architecture extension to the target architecture. Valid values for name are the same as those accepted as architectural extensions by the ``-mcpu'` commandline option.

  `.arch_extension` may be used multiple times to add or remove extensions incrementally to the architecture being compiled for.

`.arm`
  This performs the same action as .code 32.

`.pad #count`
  Generate unwinder annotations for a stack adjustment of count bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer.

`.bss`
  This directive switches to the `.bss` section.

`.cantunwind`
  Prevents unwinding through the current function. No personality routine or exception table data is required or permitted.

`.code `[16|32]``
  This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

`.cpu name`
  Select the target processor. Valid values for name are the same as for the ``-mcpu'` commandline option.

  Specifying `.cpu` clears any previously selected architecture extensions.

`name .dn register name [.type] [[index]]`
`name .qn register name [.type] [[index]]`

  The `dn` and `qn` directives are used to create typed and/or indexed register aliases for use in Advanced SIMD Extension (Neon) instructions. The former should be used to create aliases of double-precision registers, and the latter to create aliases of quad-precision registers.

  If these directives are used to create typed aliases, those aliases can be used in Neon instructions instead of writing types after the mnemonic or after each operand. For example:

              x .dn d2.f32
              y .dn d3.f32
              z .dn d4.f32[1]
              vmul x,y,z

  This is equivalent to writing the following:

              vmul.f32 d2,d3,d4[1]

  Aliases created using `dn` or `qn` can be destroyed using `unreq`.

`.eabi_attribute tag, value`
  Set the EABI object attribute tag to value.

  The tag is either an attribute number, or one of the following: `Tag_CPU_raw_name`, `Tag_CPU_name`, `Tag_CPU_arch`, `Tag_CPU_arch_profile`, `Tag_ARM_ISA_use`, `Tag_THUMB_ISA_use`, `Tag_FP_arch`, `Tag_WMMX_arch`, `Tag_Advanced_SIMD_arch`, `Tag_PCS_config`, `Tag_ABI_PCS_R9_use`, `Tag_ABI_PCS_RW_data`, `Tag_ABI_PCS_RO_data`, `Tag_ABI_PCS_GOT_use`, `Tag_ABI_PCS_wchar_t`, `Tag_ABI_FP_rounding`, `Tag_ABI_FP_denormal`, `Tag_ABI_FP_exceptions`, `Tag_ABI_FP_user_exceptions`, `Tag_ABI_FP_number_model`, `Tag_ABI_align_needed`, `Tag_ABI_align_preserved`, `Tag_ABI_enum_size`, `Tag_ABI_HardFP_use`, `Tag_ABI_VFP_args`, `Tag_ABI_WMMX_args`, `Tag_ABI_optimization_goals`, `Tag_ABI_FP_optimization_goals`, `Tag_compatibility`, `Tag_CPU_unaligned_access`, `Tag_FP_HP_extension`, `Tag_ABI_FP_16bit_format`, `Tag_MPextension_use`, `Tag_DIV_use`, `Tag_nodefaults`, `Tag_also_compatible_with`, `Tag_conformance`, `Tag_T2EE_use`, `Tag_Virtualization_use`

  The value is either a `number`, `"string"`, or `number, "string"` depending on the tag.

  Note - the following legacy values are also accepted by tag: `Tag_VFP_arch`, `Tag_ABI_align8_needed`, `Tag_ABI_align8_preserved`, `Tag_VFP_HP_extension`,

`.even`
  This directive aligns to an even-numbered address.

`.extend expression [, expression]*`
`.ldouble expression [, expression]*`
  These directives write 12byte long double floating-point values to the output section. These are not compatible with current ARM processors or ABIs.

`.fnend`
  Marks the end of a function with an unwind table entry. The unwind index table entry is created when this directive is processed.

  If no personality routine has been specified then standard personality routine 0 or 1 will be used, depending on the number of unwind opcodes required.

`.fnstart`
  Marks the start of a function with an unwind table entry.

`.force_thumb`
  This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

`.fpu name`
  Select the floating-point unit to assemble for. Valid values for name are the same as for the ``-mfpu'` commandline option.

`.handlerdata`
  Marks the end of the current function, and the start of the exception table entry for that function. Anything between this directive and the `.fnend` directive will be added to the exception table entry.

  Must be preceded by a `.personality` or `.personalityindex` directive.

`.inst opcode [ , ... ]`
`.inst.n opcode [ , ... ]`
`.inst.w opcode [ , ... ]`
  Generates the instruction corresponding to the numerical value opcode. `.inst.n` and `.inst.w` allow the Thumb instruction size to be specified explicitly, overriding the normal encoding rules.

`.ldouble expression [, expression]*`
  See `.extend`.

`.ltorg`
  This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). `GAS` maintains a separate literal pool for each section and each sub-section. The `.ltorg` directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped.

  Note - older versions of `GAS` would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools.

`.movsp reg [, #offset]`
  Tell the unwinder that reg contains an offset from the current stack pointer. If offset is not specified then it is assumed to be zero.

`.object_arch name`
  Override the architecture recorded in the EABI object attribute section. Valid values for name are the same as for the `.arch` directive. Typically this is useful when code uses runtime detection of CPU features.

`.packed expression [, expression]*`
  This directive writes 12-byte packed floating-point values to the output section. These are not compatible with current ARM processors or ABIs.

`.pad #count`
  Generate unwinder annotations for a stack adjustment of count bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer.

`.personality name`
  Sets the personality routine for the current function to name.

`.personalityindex index`
  Sets the personality routine for the current function to the EABI standard routine number index

`.pool`
  This is a synonym for .ltorg.

`name .req register name`
  This creates an alias for register name called name. For example:

              foo .req r0

`.save reglist`
  Generate unwinder annotations to restore the registers in reglist. The format of reglist is the same as the corresponding store-multiple instruction.

      core registers
        .save {r4, r5, r6, lr}
        stmfd sp!, {r4, r5, r6, lr}
      FPA registers
        .save f4, 2
        sfmfd f4, 2, [sp]!
      VFP registers
        .save {d8, d9, d10}
        fstmdx sp!, {d8, d9, d10}
      iWMMXt registers
        .save {wr10, wr11}
        wstrd wr11, [sp, #-8]!
        wstrd wr10, [sp, #-8]!
      or
        .save wr11
        wstrd wr11, [sp, #-8]!
        .save wr10
        wstrd wr10, [sp, #-8]!

`.setfp fpreg, spreg [, #offset]`
  Make all unwinder annotations relative to a frame pointer. Without this the unwinder will use offsets from the stack pointer.

  The syntax of this directive is the same as the `add` or `mov` instruction used to set the frame pointer. spreg must be either `sp` or mentioned in a previous `.movsp` directive.

      .movsp ip
      mov ip, sp
      ...
      .setfp fp, ip, #4
      add fp, ip, #4

`.secrel32 expression [, expression]*`
  This directive emits relocations that evaluate to the section-relative offset of each expression's symbol. This directive is only supported for PE targets.

`.syntax [`unified` | `divided`]`
  This directive sets the Instruction Set Syntax as described in the 9.3.2.1 Instruction Set Syntax section.

`.thumb`
  This performs the same action as .code 16.

`.thumb_func`
  This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies `.thumb`

  This directive is not neccessary when generating EABI objects. On these targets the encoding is implicit when generating Thumb code.

`.thumb_set`
  This performs the equivalent of a `.set` directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the `.thumb_func` directive does.

`.tlsdescseq tls-variable`
  This directive is used to annotate parts of an inlined TLS descriptor trampoline. Normally the trampoline is provided by the linker, and this directive is not needed.

`.unreq alias-name`
  This undefines a register alias which was previously defined using the `req`, `dn` or `qn` directives. For example:

              foo .req r0
              .unreq foo

  An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary.

`.unwind_raw offset, byte1, ...`
  Insert one of more arbitary unwind opcode bytes, which are known to adjust the stack pointer by offset bytes.

  For example `.unwind_raw 4, 0xb1, 0x01` is equivalent to `.save {r0}`

`.vsave vfp-reglist`
  Generate unwinder annotations to restore the VFP registers in vfp-reglist using FLDMD. Also works for VFPv3 registers that are to be restored using VLDM. The format of vfp-reglist is the same as the corresponding store-multiple instruction.

      VFP registers
        .vsave {d8, d9, d10}
        fstmdd sp!, {d8, d9, d10}
      VFPv3 registers
        .vsave {d15, d16, d17}
        vstm sp!, {d15, d16, d17}

  Since FLDMX and FSTMX are now deprecated, this directive should be used in favour of `.save` for saving VFP registers for ARMv6 and above.

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### 9.3.5 Opcodes

`as` implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

`NOP`

        nop

  This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

`LDR`

        ldr <register> , = <expression>

  If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

`ADR`

        adr <register> <label>

  This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

`ADRL`

        adrl <register> <label>

  This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

  If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

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### 9.3.6 Mapping Symbols

The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:

`$a`
  At the start of a region of code containing ARM instructions.

`$t`
  At the start of a region of code containing THUMB instructions.

`$d`
  At the start of a region of data.

The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.

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### 9.3.7 Unwinding

The ABI for the ARM Architecture specifies a standard format for exception unwind information. This information is used when an exception is thrown to determine where control should be transferred. In particular, the unwind information is used to determine which function called the function that threw the exception, and which function called that one, and so forth. This information is also used to restore the values of callee-saved registers in the function catching the exception.

If you are writing functions in assembly code, and those functions call other functions that throw exceptions, you must use assembly pseudo ops to ensure that appropriate exception unwind information is generated. Otherwise, if one of the functions called by your assembly code throws an exception, the run-time library will be unable to unwind the stack through your assembly code and your program will not behave correctly.

To illustrate the use of these pseudo ops, we will examine the code that G++ generates for the following C++ input:

@verbatim void callee (int *);

int caller () { int i; callee (&i); return i; }

This example does not show how to throw or catch an exception from assembly code. That is a much more complex operation and should always be done in a high-level language, such as C++, that directly supports exceptions.

The code generated by one particular version of G++ when compiling the example above is:

@verbatim _Z6callerv: .fnstart .LFB2: Function supports interworking. args = 0, pretend = 0, frame = 8 frame_needed = 1, uses_anonymous_args = 0 stmfd sp!, {fp, lr} .save {fp, lr} .LCFI0: .setfp fp, sp, #4 add fp, sp, #4 .LCFI1: .pad #8 sub sp, sp, #8 .LCFI2: sub r3, fp, #8 mov r0, r3 bl _Z6calleePi ldr r3, [fp, #-8] mov r0, r3 sub sp, fp, #4 ldmfd sp!, {fp, lr} bx lr .LFE2: .fnend

Of course, the sequence of instructions varies based on the options you pass to GCC and on the version of GCC in use. The exact instructions are not important since we are focusing on the pseudo ops that are used to generate unwind information.

An important assumption made by the unwinder is that the stack frame does not change during the body of the function. In particular, since we assume that the assembly code does not itself throw an exception, the only point where an exception can be thrown is from a call, such as the `bl` instruction above. At each call site, the same saved registers (including `lr`, which indicates the return address) must be located in the same locations relative to the frame pointer.

The `.fnstart` (see section .fnstart pseudo op) pseudo op appears immediately before the first instruction of the function while the `.fnend` (see section .fnend pseudo op) pseudo op appears immediately after the last instruction of the function. These pseudo ops specify the range of the function.

Only the order of the other pseudos ops (e.g., `.setfp` or `.pad`) matters; their exact locations are irrelevant. In the example above, the compiler emits the pseudo ops with particular instructions. That makes it easier to understand the code, but it is not required for correctness. It would work just as well to emit all of the pseudo ops other than `.fnend` in the same order, but immediately after `.fnstart`.

The `.save` (see section .save pseudo op) pseudo op indicates registers that have been saved to the stack so that they can be restored before the function returns. The argument to the `.save` pseudo op is a list of registers to save. If a register is "callee-saved" (as specified by the ABI) and is modified by the function you are writing, then your code must save the value before it is modified and restore the original value before the function returns. If an exception is thrown, the run-time library restores the values of these registers from their locations on the stack before returning control to the exception handler. (Of course, if an exception is not thrown, the function that contains the `.save` pseudo op restores these registers in the function epilogue, as is done with the `ldmfd` instruction above.)

You do not have to save callee-saved registers at the very beginning of the function and you do not need to use the `.save` pseudo op immediately following the point at which the registers are saved. However, if you modify a callee-saved register, you must save it on the stack before modifying it and before calling any functions which might throw an exception. And, you must use the `.save` pseudo op to indicate that you have done so.

The `.pad` (see section .pad) pseudo op indicates a modification of the stack pointer that does not save any registers. The argument is the number of bytes (in decimal) that are subtracted from the stack pointer. (On ARM CPUs, the stack grows downwards, so subtracting from the stack pointer increases the size of the stack.)

The `.setfp` (see section .setfp pseudo op) pseudo op indicates the register that contains the frame pointer. The first argument is the register that is set, which is typically `fp`. The second argument indicates the register from which the frame pointer takes its value. The third argument, if present, is the value (in decimal) added to the register specified by the second argument to compute the value of the frame pointer. You should not modify the frame pointer in the body of the function.

If you do not use a frame pointer, then you should not use the `.setfp` pseudo op. If you do not use a frame pointer, then you should avoid modifying the stack pointer outside of the function prologue. Otherwise, the run-time library will be unable to find saved registers when it is unwinding the stack.

The pseudo ops described above are sufficient for writing assembly code that calls functions which may throw exceptions. If you need to know more about the object-file format used to represent unwind information, you may consult the Exception Handling ABI for the ARM Architecture available from http://infocenter.arm.com.

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## 9.4 AVR Dependent Features

> 9.4.1 Options |  |
> 9.4.2 Syntax |  |
> 9.4.3 Opcodes |  |

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### 9.4.1 Options

`-mmcu=mcu`
  Specify ATMEL AVR instruction set or MCU type.

  Instruction set avr1 is for the minimal AVR core, not supported by the C compiler, only for assembler programs (MCU types: at90s1200, attiny11, attiny12, attiny15, attiny28).

  Instruction set avr2 (default) is for the classic AVR core with up to 8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, at90s8535).

  Instruction set avr25 is for the classic AVR core with up to 8K program memory space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, at86rf401).

  Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711).

  Instruction set avr31 is for the classic AVR core with exactly 128K program memory space (MCU types: atmega103, at43usb320).

  Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP instructions (MCU types: attiny167, at90usb82, at90usb162, atmega8u2, atmega16u2, atmega32u2).

  Instruction set avr4 is for the enhanced AVR core with up to 8K program memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6289).

  Instruction set avr5 is for the enhanced AVR core with up to 128K program memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega165, atmega165a, atmega165p, atmega168, atmega168a, atmega168p, atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, atmega324p, atmega325, atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega640, atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, atmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, at90scr100).

  Instruction set avr51 is for the enhanced AVR core with exactly 128K program memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000).

  Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).

  Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1).

  Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program memory space and greater than 64K data space (MCU types: none).

  Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).

  Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program memory space and greater than 64K data space (MCU types: atxmega64a1, atxmega64a1u).

  Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program memory space and less than 64K data space (MCU types: atxmega128a3, atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, atxmega192d3).

  Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program memory space and greater than 64K data space (MCU types: atxmega128a1, atxmega128a1u).

`-mall-opcodes`
  Accept all AVR opcodes, even if not supported by `-mmcu`.

`-mno-skip-bug`
  This option disable warnings for skipping two-word instructions.

`-mno-wrap`
  This option reject `rjmp/rcall` instructions with 8K wrap-around.

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### 9.4.2 Syntax

> 9.4.2.1 Special Characters |  |
> 9.4.2.2 Register Names |  |
> 9.4.2.3 Relocatable Expression Modifiers |  |

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#### 9.4.2.1 Special Characters

The presence of a ``;'` anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``$'` character can be used instead of a newline to separate statements.

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#### 9.4.2.2 Register Names

The AVR has 32 x 8-bit general purpose working registers ``r0'`, ``r1'`, ... ``r31'`. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit ``X'`, ``Y'` and ``Z'` - registers.

    X = r26:r27
    Y = r28:r29
    Z = r30:r31

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#### 9.4.2.3 Relocatable Expression Modifiers

The assembler supports several modifiers when using relocatable addresses in AVR instruction operands. The general syntax is the following:

    modifier(relocatable-expression)

`lo8`

  This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression.

`hi8`

  This modifier allows you to use bits 7 through 15 of an address expression as 8 bit relocatable expression. This is useful with, for example, the AVR ``ldi'` instruction and ``lo8'` modifier.

  For example

      ldi r26, lo8(sym+10)
      ldi r27, hi8(sym+10)

`hh8`

  This modifier allows you to use bits 16 through 23 of an address expression as 8 bit relocatable expression. Also, can be useful for loading 32 bit constants.

`hlo8`

  Synonym of ``hh8'`.

`hhi8`

  This modifier allows you to use bits 24 through 31 of an expression as 8 bit expression. This is useful with, for example, the AVR ``ldi'` instruction and ``lo8'`, ``hi8'`, ``hlo8'`, ``hhi8'`, modifier.

  For example

      ldi r26, lo8(285774925)
      ldi r27, hi8(285774925)
      ldi r28, hlo8(285774925)
      ldi r29, hhi8(285774925)
      ; r29,r28,r27,r26 = 285774925

`pm_lo8`

  This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory. The using of ``pm_lo8'` similar to ``lo8'`.

`pm_hi8`

  This modifier allows you to use bits 8 through 15 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory.

`pm_hh8`

  This modifier allows you to use bits 15 through 23 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory.

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### 9.4.3 Opcodes

For detailed information on the AVR machine instruction set, see www.atmel.com/products/AVR.

`as` implements all the standard AVR opcodes. The following table summarizes the AVR opcodes, and their arguments.

    Legend:
       r   any register
       d   `ldi' register (r16-r31)
       v   `movw' even register (r0, r2, ..., r28, r30)
       a   `fmul' register (r16-r23)
       w   `adiw' register (r24,r26,r28,r30)
       e   pointer registers (X,Y,Z)
       b   base pointer register and displacement ([YZ]+disp)
       z   Z pointer register (for [e]lpm Rd,Z[+])
       M   immediate value from 0 to 255
       n   immediate value from 0 to 255 ( n = ~M ). Relocation impossible
       s   immediate value from 0 to 7
       P   Port address value from 0 to 63. (in, out)
       p   Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
       K   immediate value from 0 to 63 (used in `adiw', `sbiw')
       i   immediate value
       l   signed pc relative offset from -64 to 63
       L   signed pc relative offset from -2048 to 2047
       h   absolute code address (call, jmp)
       S   immediate value from 0 to 7 (S = s << 4)
       ?   use this opcode entry if no parameters, else use next opcode entry

    1001010010001000   clc
    1001010011011000   clh
    1001010011111000   cli
    1001010010101000   cln
    1001010011001000   cls
    1001010011101000   clt
    1001010010111000   clv
    1001010010011000   clz
    1001010000001000   sec
    1001010001011000   seh
    1001010001111000   sei
    1001010000101000   sen
    1001010001001000   ses
    1001010001101000   set
    1001010000111000   sev
    1001010000011000   sez
    100101001SSS1000   bclr    S
    100101000SSS1000   bset    S
    1001010100001001   icall
    1001010000001001   ijmp
    1001010111001000   lpm     ?
    1001000ddddd010+   lpm     r,z
    1001010111011000   elpm    ?
    1001000ddddd011+   elpm    r,z
    0000000000000000   nop
    1001010100001000   ret
    1001010100011000   reti
    1001010110001000   sleep
    1001010110011000   break
    1001010110101000   wdr
    1001010111101000   spm
    000111rdddddrrrr   adc     r,r
    000011rdddddrrrr   add     r,r
    001000rdddddrrrr   and     r,r
    000101rdddddrrrr   cp      r,r
    000001rdddddrrrr   cpc     r,r
    000100rdddddrrrr   cpse    r,r
    001001rdddddrrrr   eor     r,r
    001011rdddddrrrr   mov     r,r
    100111rdddddrrrr   mul     r,r
    001010rdddddrrrr   or      r,r
    000010rdddddrrrr   sbc     r,r
    000110rdddddrrrr   sub     r,r
    001001rdddddrrrr   clr     r
    000011rdddddrrrr   lsl     r
    000111rdddddrrrr   rol     r
    001000rdddddrrrr   tst     r
    0111KKKKddddKKKK   andi    d,M
    0111KKKKddddKKKK   cbr     d,n
    1110KKKKddddKKKK   ldi     d,M
    11101111dddd1111   ser     d
    0110KKKKddddKKKK   ori     d,M
    0110KKKKddddKKKK   sbr     d,M
    0011KKKKddddKKKK   cpi     d,M
    0100KKKKddddKKKK   sbci    d,M
    0101KKKKddddKKKK   subi    d,M
    1111110rrrrr0sss   sbrc    r,s
    1111111rrrrr0sss   sbrs    r,s
    1111100ddddd0sss   bld     r,s
    1111101ddddd0sss   bst     r,s
    10110PPdddddPPPP   in      r,P
    10111PPrrrrrPPPP   out     P,r
    10010110KKddKKKK   adiw    w,K
    10010111KKddKKKK   sbiw    w,K
    10011000pppppsss   cbi     p,s
    10011010pppppsss   sbi     p,s
    10011001pppppsss   sbic    p,s
    10011011pppppsss   sbis    p,s
    111101lllllll000   brcc    l
    111100lllllll000   brcs    l
    111100lllllll001   breq    l
    111101lllllll100   brge    l
    111101lllllll101   brhc    l
    111100lllllll101   brhs    l
    111101lllllll111   brid    l
    111100lllllll111   brie    l
    111100lllllll000   brlo    l
    111100lllllll100   brlt    l
    111100lllllll010   brmi    l
    111101lllllll001   brne    l
    111101lllllll010   brpl    l
    111101lllllll000   brsh    l
    111101lllllll110   brtc    l
    111100lllllll110   brts    l
    111101lllllll011   brvc    l
    111100lllllll011   brvs    l
    111101lllllllsss   brbc    s,l
    111100lllllllsss   brbs    s,l
    1101LLLLLLLLLLLL   rcall   L
    1100LLLLLLLLLLLL   rjmp    L
    1001010hhhhh111h   call    h
    1001010hhhhh110h   jmp     h
    1001010rrrrr0101   asr     r
    1001010rrrrr0000   com     r
    1001010rrrrr1010   dec     r
    1001010rrrrr0011   inc     r
    1001010rrrrr0110   lsr     r
    1001010rrrrr0001   neg     r
    1001000rrrrr1111   pop     r
    1001001rrrrr1111   push    r
    1001010rrrrr0111   ror     r
    1001010rrrrr0010   swap    r
    00000001ddddrrrr   movw    v,v
    00000010ddddrrrr   muls    d,d
    000000110ddd0rrr   mulsu   a,a
    000000110ddd1rrr   fmul    a,a
    000000111ddd0rrr   fmuls   a,a
    000000111ddd1rrr   fmulsu  a,a
    1001001ddddd0000   sts     i,r
    1001000ddddd0000   lds     r,i
    10o0oo0dddddbooo   ldd     r,b
    100!000dddddee-+   ld      r,e
    10o0oo1rrrrrbooo   std     b,r
    100!001rrrrree-+   st      e,r
    1001010100011001   eicall
    1001010000011001   eijmp

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## 9.5 Blackfin Dependent Features

> 9.5.1 Options |  | Blackfin Options
> 9.5.2 Syntax |  | Blackfin Syntax
> 9.5.3 Directives |  | Blackfin Directives

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### 9.5.1 Options

`-mcpu=processor[-sirevision]`
  This option specifies the target processor. The optional sirevision is not used in assembler. It's here such that GCC can easily pass down its `-mcpu=` option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: `bf504`, `bf506`, `bf512`, `bf514`, `bf516`, `bf518`, `bf522`, `bf523`, `bf524`, `bf525`, `bf526`, `bf527`, `bf531`, `bf532`, `bf533`, `bf534`, `bf535` (not implemented yet), `bf536`, `bf537`, `bf538`, `bf539`, `bf542`, `bf542m`, `bf544`, `bf544m`, `bf547`, `bf547m`, `bf548`, `bf548m`, `bf549`, `bf549m`, `bf561`, and `bf592`.

`-mfdpic`
  Assemble for the FDPIC ABI.

`-mno-fdpic`
`-mnopic`
  Disable -mfdpic.

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### 9.5.2 Syntax

`Special Characters`
  Assembler input is free format and may appear anywhere on the line. One instruction may extend across multiple lines or more than one instruction may appear on the same line. White space (space, tab, comments or newline) may appear anywhere between tokens. A token must not have embedded spaces. Tokens include numbers, register names, keywords, user identifiers, and also some multicharacter special symbols like "+=", "/*" or "||".

  Comments are introduced by the ``#'` character and extend to the end of the current line. If the ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

`Instruction Delimiting`
  A semicolon must terminate every instruction. Sometimes a complete instruction will consist of more than one operation. There are two cases where this occurs. The first is when two general operations are combined. Normally a comma separates the different parts, as in

      a0= r3.h * r2.l, a1 = r3.l * r2.h ;

  The second case occurs when a general instruction is combined with one or two memory references for joint issue. The latter portions are set off by a "||" token.

      a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];

  Multiple instructions can occur on the same line. Each must be terminated by a semicolon character.

`Register Names`

  The assembler treats register names and instruction keywords in a case insensitive manner. User identifiers are case sensitive. Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the assembler.

  Register names are reserved and may not be used as program identifiers.

  Some operations (such as "Move Register") require a register pair. Register pairs are always data registers and are denoted using a colon, eg., R3:2. The larger number must be written firsts. Note that the hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.

  Some instructions (such as --SP (Push Multiple)) require a group of adjacent registers. Adjacent registers are denoted in the syntax by the range enclosed in parentheses and separated by a colon, eg., (R7:3). Again, the larger number appears first.

  Portions of a particular register may be individually specified. This is written with a dot (".") following the register name and then a letter denoting the desired portion. For 32-bit registers, ".H" denotes the most significant ("High") portion. ".L" denotes the least-significant portion. The subdivisions of the 40-bit registers are described later.

`Accumulators`
  The set of 40-bit registers A1 and A0 that normally contain data that is being manipulated. Each accumulator can be accessed in four ways.

  `one 40-bit register`
    The register will be referred to as A1 or A0.
  `one 32-bit register`
    The registers are designated as A1.W or A0.W.
  `two 16-bit registers`
    The registers are designated as A1.H, A1.L, A0.H or A0.L.
  `one 8-bit register`
    The registers are designated as A1.X or A0.X for the bits that extend beyond bit 31.

`Data Registers`
  The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that normally contain data for manipulation. These are abbreviated as D-register or Dreg. Data registers can be accessed as 32-bit registers or as two independent 16-bit registers. The least significant 16 bits of each register is called the "low" half and is designated with ".L" following the register name. The most significant 16 bits are called the "high" half and is designated with ".H" following the name.

         R7.L, r2.h, r4.L, R0.H

`Pointer Registers`
  The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that normally contain byte addresses of data structures. These are abbreviated as P-register or Preg.

      p2, p5, fp, sp

`Stack Pointer SP`
  The stack pointer contains the 32-bit address of the last occupied byte location in the stack. The stack grows by decrementing the stack pointer.

`Frame Pointer FP`
  The frame pointer contains the 32-bit address of the previous frame pointer in the stack. It is located at the top of a frame.

`Loop Top`
  LT0 and LT1. These registers contain the 32-bit address of the top of a zero overhead loop.

`Loop Count`
  LC0 and LC1. These registers contain the 32-bit counter of the zero overhead loop executions.

`Loop Bottom`
  LB0 and LB1. These registers contain the 32-bit address of the bottom of a zero overhead loop.

`Index Registers`
  The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte addresses of data structures. Abbreviated I-register or Ireg.

`Modify Registers`
  The set of 32-bit registers (M0, M1, M2, M3) that normally contain offset values that are added and subtracted to one of the index registers. Abbreviated as Mreg.

`Length Registers`
  The set of 32-bit registers (L0, L1, L2, L3) that normally contain the length in bytes of the circular buffer. Abbreviated as Lreg. Clear the Lreg to disable circular addressing for the corresponding Ireg.

`Base Registers`
  The set of 32-bit registers (B0, B1, B2, B3) that normally contain the base address in bytes of the circular buffer. Abbreviated as Breg.

`Floating Point`
  The Blackfin family has no hardware floating point but the .float directive generates ieee floating point numbers for use with software floating point libraries.

`Blackfin Opcodes`
  For detailed information on the Blackfin machine instruction set, see the Blackfin(r) Processor Instruction Set Reference.

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### 9.5.3 Directives

The following directives are provided for compatibility with the VDSP assembler.

`.byte2`
  Initializes a two byte data object.

  This maps to the `.short` directive.

`.byte4`
  Initializes a four byte data object.

  This maps to the `.int` directive.

`.db`
  Initializes a single byte data object.

  This directive is a synonym for `.byte`.

`.dw`
  Initializes a two byte data object.

  This directive is a synonym for `.byte2`.

`.dd`
  Initializes a four byte data object.

  This directive is a synonym for `.byte4`.

`.var`
  Define and initialize a 32 bit data object.

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## 9.6 CR16 Dependent Features

> 9.6.1 CR16 Operand Qualifiers |  | CR16 Machine Operand Qualifiers
> 9.6.2 CR16 Syntax |  | Syntax for the CR16

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### 9.6.1 CR16 Operand Qualifiers

The National Semiconductor CR16 target of `as` has a few machine dependent operand qualifiers.

Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The `@` is required. CR16 architecture uses one of the following expression qualifiers:

`s`
  - `Specifies expression operand type as small`
`m`
  - `Specifies expression operand type as medium`
`l`
  - `Specifies expression operand type as large`
`c`
  - `Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.`
`got/GOT`
  - `Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time`
`cgot/cGOT`
  - `Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.`

CR16 target operand qualifiers and its size (in bits):

``Immediate Operand: s'`
  4 bits.

``Immediate Operand: m'`
  16 bits, for movb and movw instructions.

``Immediate Operand: m'`
  20 bits, movd instructions.

``Immediate Operand: l'`
  32 bits.

``Absolute Operand: s'`
  Illegal specifier for this operand.

``Absolute Operand: m'`
  20 bits, movd instructions.

``Displacement Operand: s'`
  8 bits.

``Displacement Operand: m'`
  16 bits.

``Displacement Operand: l'`
  24 bits.

For example:

    1   movw $_myfun@c,r1

        This loads the address of _myfun, shifted right by 1, into r1.

    2   movd $_myfun@c,(r2,r1)

        This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.

    3   _myfun_ptr:
        .long _myfun@c
        loadd _myfun_ptr, (r1,r0)
        jal (r1,r0)

        This .long directive, the address of _myfunc, shifted right by 1 at link time.

    4   loadd  _data1@GOT(r12), (r1,r0)

        This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.

    5   loadd  _myfunc@cGOT(r12), (r1,r0)

        This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.

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### 9.6.2 CR16 Syntax

> 9.6.2.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.6.2.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line. If the ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.7 CRIS Dependent Features

> 9.7.1 Command-line Options |  |
> 9.7.2 Instruction expansion |  |
> 9.7.3 Symbols |  |
> 9.7.4 Syntax |  |

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### 9.7.1 Command-line Options

The CRIS version of `as` has these machine-dependent command-line options.

The format of the generated object files can be either ELF or a.out, specified by the command-line options ``--emulation=crisaout'` and ``--emulation=criself'`. The default is ELF (criself), unless `as` has been configured specifically for a.out by using the configuration name `cris-axis-aout`.

There are two different link-incompatible ELF object file variants for CRIS, for use in environments where symbols are expected to be prefixed by a leading ``_'` character and for environments without such a symbol prefix. The variant used for GNU/Linux port has no symbol prefix. Which variant to produce is specified by either of the options ``--underscore'` and ``--no-underscore'`. The default is ``--underscore'`. Since symbols in CRIS a.out objects are expected to have a ``_'` prefix, specifying ``--no-underscore'` when generating a.out objects is an error. Besides the object format difference, the effect of this option is to parse register names differently (see crisnous). The ``--no-underscore'` option makes a ``$'` register prefix mandatory.

The option ``--pic'` must be passed to `as` in order to recognize the symbol syntax used for ELF (SVR4 PIC) position-independent-code (see crispic). This will also affect expansion of instructions. The expansion with ``--pic'` will use PC-relative rather than (slightly faster) absolute addresses in those expansions. This option is only valid when generating ELF format object files.

The option ``--march=architecture'` specifies the recognized instruction set and recognized register names. It also controls the architecture type of the object file. Valid values for architecture are:

`v0_v10`
  All instructions and register names for any architecture variant in the set v0...v10 are recognized. This is the default if the target is configured as cris-*.

`v10`
  Only instructions and register names for CRIS v10 (as found in ETRAX 100 LX) are recognized. This is the default if the target is configured as crisv10-*.

`v32`
  Only instructions and register names for CRIS v32 (code name Guinness) are recognized. This is the default if the target is configured as crisv32-*. This value implies ``--no-mul-bug-abort'`. (A subsequent ``--mul-bug-abort'` will turn it back on.)

`common_v10_v32`
  Only instructions with register names and addressing modes with opcodes common to the v10 and v32 are recognized.

When ``-N'` is specified, `as` will emit a warning when a 16-bit branch instruction is expanded into a 32-bit multiple-instruction construct (see section 9.7.2 Instruction expansion).

Some versions of the CRIS v10, for example in the Etrax 100 LX, contain a bug that causes destabilizing memory accesses when a multiply instruction is executed with certain values in the first operand just before a cache-miss. When the ``--mul-bug-abort'` command line option is active (the default value), `as` will refuse to assemble a file containing a multiply instruction at a dangerous offset, one that could be the last on a cache-line, or is in a section with insufficient alignment. This placement checking does not catch any case where the multiply instruction is dangerously placed because it is located in a delay-slot. The ``--mul-bug-abort'` command line option turns off the checking.

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### 9.7.2 Instruction expansion

`as` will silently choose an instruction that fits the operand size for ``[register+constant]'` operands. For example, the offset `127` in `move.d [r3+127],r4` fits in an instruction using a signed-byte offset. Similarly, `move.d [r2+32767],r1` will generate an instruction using a 16-bit offset. For symbolic expressions and constants that do not fit in 16 bits including the sign bit, a 32-bit offset is generated.

For branches, `as` will expand from a 16-bit branch instruction into a sequence of instructions that can reach a full 32-bit address. Since this does not correspond to a single instruction, such expansions can optionally be warned about. See section 9.7.1 Command-line Options.

If the operand is found to fit the range, a `lapc` mnemonic will translate to a `lapcq` instruction. Use `lapc.d` to force the 32-bit `lapc` instruction.

Similarly, the `addo` mnemonic will translate to the shortest fitting instruction of `addoq`, `addo.w` and `addo.d`, when used with a operand that is a constant known at assembly time.

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### 9.7.3 Symbols

Some symbols are defined by the assembler. They're intended to be used in conditional assembly, for example:

     .if ..asm.arch.cris.v32
     code for CRIS v32
     .elseif ..asm.arch.cris.common_v10_v32
     code common to CRIS v32 and CRIS v10
     .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
     code for v10
     .else
     .error "Code needs to be added here."
     .endif

These symbols are defined in the assembler, reflecting command-line options, either when specified or the default. They are always defined, to 0 or 1.

`..asm.arch.cris.any_v0_v10`
  This symbol is non-zero when ``--march=v0_v10'` is specified or the default.

`..asm.arch.cris.common_v10_v32`
  Set according to the option ``--march=common_v10_v32'`.

`..asm.arch.cris.v10`
  Reflects the option ``--march=v10'`.

`..asm.arch.cris.v32`
  Corresponds to ``--march=v10'`.

Speaking of symbols, when a symbol is used in code, it can have a suffix modifying its value for use in position-independent code. See section 9.7.4.2 Symbols in position-independent code.

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### 9.7.4 Syntax

There are different aspects of the CRIS assembly syntax.

> 9.7.4.1 Special Characters |  |
> 9.7.4.2 Symbols in position-independent code |  | Position-Independent Code Symbols
> 9.7.4.3 Register names |  | Register Names
> 9.7.4.4 Assembler Directives |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.7.4.1 Special Characters

The character ``#'` is a line comment character. It starts a comment if and only if it is placed at the beginning of a line.

A ``;'` character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored.

A ``@'` character is handled as a line separator equivalent to a logical new-line character (except in a comment), so separate instructions can be specified on a single line.

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#### 9.7.4.2 Symbols in position-independent code

When generating position-independent code (SVR4 PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol suffixes are used to specify what kind of run-time symbol lookup will be used, expressed in the object as different relocation types. Usually, all absolute symbol values must be located in a table, the global offset table, leaving the code position-independent; independent of values of global symbols and independent of the address of the code. The suffix modifies the value of the symbol, into for example an index into the global offset table where the real symbol value is entered, or a PC-relative value, or a value relative to the start of the global offset table. All symbol suffixes start with the character ``:'` (omitted in the list below). Every symbol use in code or a read-only section must therefore have a PIC suffix to enable a useful shared library to be created. Usually, these constructs must not be used with an additive constant offset as is usually allowed, i.e. no 4 as in `symbol + 4` is allowed. This restriction is checked at link-time, not at assembly-time.

`GOT`

  Attaching this suffix to a symbol in an instruction causes the symbol to be entered into the global offset table. The value is a 32-bit index for that symbol into the global offset table. The name of the corresponding relocation is ``R_CRIS_32_GOT'`. Example: `move.d [$r0+extsym:GOT],$r9`

`GOT16`

  Same as for ``GOT'`, but the value is a 16-bit index into the global offset table. The corresponding relocation is ``R_CRIS_16_GOT'`. Example: `move.d [$r0+asymbol:GOT16],$r10`

`PLT`

  This suffix is used for function symbols. It causes a procedure linkage table, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to look up and set the value of the symbol the first time the function is called (at latest; depending environment variables). It is only safe to leave the symbol unresolved this way if all references are function calls. The name of the relocation is ``R_CRIS_32_PLT_PCREL'`. Example: `add.d fnname:PLT,$pc`

`PLTG`

  Like PLT, but the value is relative to the beginning of the global offset table. The relocation is ``R_CRIS_32_PLT_GOTREL'`. Example: `move.d fnname:PLTG,$r3`

`GOTPLT`

  Similar to ``PLT'`, but the value of the symbol is a 32-bit index into the global offset table. This is somewhat of a mix between the effect of the ``GOT'` and the ``PLT'` suffix; the difference to ``GOT'` is that there will be a procedure linkage table entry created, and that the symbol is assumed to be a function entry and will be resolved by the run-time resolver as with ``PLT'`. The relocation is ``R_CRIS_32_GOTPLT'`. Example: `jsr [$r0+fnname:GOTPLT]`

`GOTPLT16`

  A variant of ``GOTPLT'` giving a 16-bit value. Its relocation name is ``R_CRIS_16_GOTPLT'`. Example: `jsr [$r0+fnname:GOTPLT16]`

`GOTOFF`

  This suffix must only be attached to a local symbol, but may be used in an expression adding an offset. The value is the address of the symbol relative to the start of the global offset table. The relocation name is ``R_CRIS_32_GOTREL'`. Example: `move.d [$r0+localsym:GOTOFF],r3`

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#### 9.7.4.3 Register names

A ``$'` character may always prefix a general or special register name in an instruction operand but is mandatory when the option ``--no-underscore'` is specified or when the `.syntax register_prefix` directive is in effect (see crisnous). Register names are case-insensitive.

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#### 9.7.4.4 Assembler Directives

There are a few CRIS-specific pseudo-directives in addition to the generic ones. See section 7. Assembler Directives. Constants emitted by pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS.

`.dword EXPRESSIONS`

  The `.dword` directive is a synonym for `.int`, expecting zero or more EXPRESSIONS, separated by commas. For each expression, a 32-bit little-endian constant is emitted.

`.syntax ARGUMENT`
  The `.syntax` directive takes as ARGUMENT one of the following case-sensitive choices.

  `no_register_prefix`

    The `.syntax no_register_prefix` directive makes a ``$'` character prefix on all registers optional. It overrides a previous setting, including the corresponding effect of the option ``--no-underscore'`. If this directive is used when ordinary symbols do not have a ``_'` character prefix, care must be taken to avoid ambiguities whether an operand is a register or a symbol; using symbols with names the same as general or special registers then invoke undefined behavior.

  `register_prefix`

    This directive makes a ``$'` character prefix on all registers mandatory. It overrides a previous setting, including the corresponding effect of the option ``--underscore'`.

  `leading_underscore`

    This is an assertion directive, emitting an error if the ``--no-underscore'` option is in effect.

  `no_leading_underscore`

    This is the opposite of the `.syntax leading_underscore` directive and emits an error if the option ``--underscore'` is in effect.

`.arch ARGUMENT`
  This is an assertion directive, giving an error if the specified ARGUMENT is not the same as the specified or default value for the ``--march=architecture'` option (see march-option).

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## 9.8 D10V Dependent Features

> 9.8.1 D10V Options |  |
> 9.8.2 Syntax |  |
> 9.8.3 Floating Point |  |
> 9.8.4 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.8.1 D10V Options

The Mitsubishi D10V version of `as` has a few machine dependent options.

``-O'`
  The D10V can often execute two sub-instructions in parallel. When this option is used, `as` will attempt to optimize its output by detecting when instructions can be executed in parallel.
``--nowarnswap'`
  To optimize execution performance, `as` will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.
``--gstabs-packing'`
``--no-gstabs-packing'`
  `as` packs adjacent short instructions into a single packed instruction. ``--no-gstabs-packing'` turns instruction packing off if ``--gstabs'` is specified as well; ``--gstabs-packing'` (the default) turns instruction packing on even when ``--gstabs'` is specified.

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### 9.8.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

> 9.8.2.1 Size Modifiers |  |
> 9.8.2.2 Sub-Instructions |  |
> 9.8.2.3 Special Characters |  |
> 9.8.2.4 Register Names |  |
> 9.8.2.5 Addressing Modes |  |
> 9.8.2.6 @WORD Modifier |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.8.2.1 Size Modifiers

The D10V version of `as` uses the instruction names in the D10V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as` will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either ``.s'` (short) or ``.l'` (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write ``bra.s foo'`. Objdump and GDB will always append ``.s'` or ``.l'` to instructions which have both short and long forms.

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#### 9.8.2.2 Sub-Instructions

The D10V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

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#### 9.8.2.3 Special Characters

A semicolon (``;'`) can be used anywhere on a line to start a comment that extends to the end of the line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially. To specify the executing order, use the following symbols:

``->'`
  Sequential with instruction on the left first.
``<-'`
  Sequential with instruction on the right first.
``||'`
  Parallel

The D10V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

`abs a1 -> abs r0`
  Execute these sequentially. The instruction on the right is in the right container and is executed second.
`abs r0 <- abs a1`
  Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.
`ld2w r2,@r8+ || mac a0,r0,r7`
  Execute these in parallel.
`ld2w r2,@r8+ ||`
`mac a0,r0,r7`
  Two-line format. Execute these in parallel.
`ld2w r2,@r8+`
`mac a0,r0,r7`
  Two-line format. Execute these sequentially. Assembler will put them in the proper containers.
`ld2w r2,@r8+ ->`
`mac a0,r0,r7`
  Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

Since ``$'` has no special meaning, you may use it in symbol names.

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#### 9.8.2.4 Register Names

You can use the predefined symbols ``r0'` through ``r15'` to refer to the D10V registers. You can also use ``sp'` as an alias for ``r15'`. The accumulators are ``a0'` and ``a1'`. There are special register-pair names that may optionally be used in opcodes that require even-numbered registers. Register names are not case sensitive.

Register Pairs

`r0-r1`
`r2-r3`
`r4-r5`
`r6-r7`
`r8-r9`
`r10-r11`
`r12-r13`
`r14-r15`

The D10V also has predefined symbols for these control registers and status bits:

`psw`
  Processor Status Word
`bpsw`
  Backup Processor Status Word
`pc`
  Program Counter
`bpc`
  Backup Program Counter
`rpt_c`
  Repeat Count
`rpt_s`
  Repeat Start address
`rpt_e`
  Repeat End address
`mod_s`
  Modulo Start address
`mod_e`
  Modulo End address
`iba`
  Instruction Break Address
`f0`
  Flag 0
`f1`
  Flag 1
`c`
  Carry flag

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#### 9.8.2.5 Addressing Modes

`as` understands the following addressing modes for the D10V. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct
`@Rn`
  Register indirect
`@Rn+`
  Register indirect with post-increment
`@Rn-`
  Register indirect with post-decrement
`@-SP`
  Register indirect with pre-decrement
`@(disp, Rn)`
  Register indirect with displacement
`addr`
  PC relative address (for branch or rep).
`#imm`
  Immediate data (the ``#'` is optional and ignored)

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#### 9.8.2.6 @WORD Modifier

Any symbol followed by `@word` will be replaced by the symbol's value shifted right by 2. This is used in situations such as loading a register with the address of a function (or any other code fragment). For example, if you want to load a register with the location of the function `main` then jump to that function, you could do it as follows:

    ldi     r2, main@word
    jmp     r2

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### 9.8.3 Floating Point

The D10V has no hardware floating point, but the `.float` and `.double` directives generates IEEE floating-point numbers for compatibility with other development tools.

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### 9.8.4 Opcodes

For detailed information on the D10V machine instruction set, see D10V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). `as` implements all the standard D10V opcodes. The only changes are those described in the section on size modifiers

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## 9.9 D30V Dependent Features

> 9.9.1 D30V Options |  |
> 9.9.2 Syntax |  |
> 9.9.3 Floating Point |  |
> 9.9.4 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.9.1 D30V Options

The Mitsubishi D30V version of `as` has a few machine dependent options.

``-O'`
  The D30V can often execute two sub-instructions in parallel. When this option is used, `as` will attempt to optimize its output by detecting when instructions can be executed in parallel.

``-n'`
  When this option is used, `as` will issue a warning every time it adds a nop instruction.

``-N'`
  When this option is used, `as` will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

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### 9.9.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

> 9.9.2.1 Size Modifiers |  |
> 9.9.2.2 Sub-Instructions |  |
> 9.9.2.3 Special Characters |  |
> 9.9.2.4 Guarded Execution |  |
> 9.9.2.5 Register Names |  |
> 9.9.2.6 Addressing Modes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.9.2.1 Size Modifiers

The D30V version of `as` uses the instruction names in the D30V Architecture Manual. However, the names in the manual are sometimes ambiguous. There are instruction names that can assemble to a short or long form opcode. How does the assembler pick the correct form? `as` will always pick the smallest form if it can. When dealing with a symbol that is not defined yet when a line is being assembled, it will always use the long form. If you need to force the assembler to use either the short or long form of the instruction, you can append either ``.s'` (short) or ``.l'` (long) to it. For example, if you are writing an assembly program and you want to do a branch to a symbol that is defined later in your program, you can write ``bra.s foo'`. Objdump and GDB will always append ``.s'` or ``.l'` to instructions which have both short and long forms.

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#### 9.9.2.2 Sub-Instructions

The D30V assembler takes as input a series of instructions, either one-per-line, or in the special two-per-line format described in the next section. Some of these instructions will be short-form or sub-instructions. These sub-instructions can be packed into a single instruction. The assembler will do this automatically. It will also detect when it should not pack instructions. For example, when a label is defined, the next instruction will never be packaged with the previous one. Whenever a branch and link instruction is called, it will not be packaged with the next instruction so the return address will be valid. Nops are automatically inserted when necessary.

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

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#### 9.9.2.3 Special Characters

A semicolon (``;'`) can be used anywhere on a line to start a comment that extends to the end of the line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Sub-instructions may be executed in order, in reverse-order, or in parallel. Instructions listed in the standard one-per-line format will be executed sequentially unless you use the ``-O'` option.

To specify the executing order, use the following symbols:

``->'`
  Sequential with instruction on the left first.

``<-'`
  Sequential with instruction on the right first.

``||'`
  Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

`abs r2,r3 -> abs r4,r5`
  Execute these sequentially. The instruction on the right is in the right container and is executed second.

`abs r2,r3 <- abs r4,r5`
  Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

`abs r2,r3 || abs r4,r5`
  Execute these in parallel.

`ldw r2,@(r3,r4) ||`
`mulx r6,r8,r9`
  Two-line format. Execute these in parallel.

`mulx a0,r8,r9`
`stw r2,@(r3,r4)`
  Two-line format. Execute these sequentially unless ``-O'` option is used. If the ``-O'` option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the ``stw'` instruction in left container and the ``mulx'` instruction in the right container.

`stw r2,@(r3,r4) ->`
`mulx a0,r8,r9`
  Two-line format. Execute the ``stw'` instruction followed by the ``mulx'` instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

`stw r2,@(r3,r4) <-`
`mulx a0,r8,r9`
  Same as previous example, except that the ``mulx'` instruction is executed before the ``stw'` instruction.

Since ``$'` has no special meaning, you may use it in symbol names.

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#### 9.9.2.4 Guarded Execution

`as` supports the full range of guarded execution directives for each instruction. Just append the directive after the instruction proper. The directives are:

``/tx'`
  Execute the instruction if flag f0 is true.
``/fx'`
  Execute the instruction if flag f0 is false.
``/xt'`
  Execute the instruction if flag f1 is true.
``/xf'`
  Execute the instruction if flag f1 is false.
``/tt'`
  Execute the instruction if both flags f0 and f1 are true.
``/tf'`
  Execute the instruction if flag f0 is true and flag f1 is false.

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#### 9.9.2.5 Register Names

You can use the predefined symbols ``r0'` through ``r63'` to refer to the D30V registers. You can also use ``sp'` as an alias for ``r63'` and ``link'` as an alias for ``r62'`. The accumulators are ``a0'` and ``a1'`.

The D30V also has predefined symbols for these control registers and status bits:

`psw`
  Processor Status Word
`bpsw`
  Backup Processor Status Word
`pc`
  Program Counter
`bpc`
  Backup Program Counter
`rpt_c`
  Repeat Count
`rpt_s`
  Repeat Start address
`rpt_e`
  Repeat End address
`mod_s`
  Modulo Start address
`mod_e`
  Modulo End address
`iba`
  Instruction Break Address
`f0`
  Flag 0
`f1`
  Flag 1
`f2`
  Flag 2
`f3`
  Flag 3
`f4`
  Flag 4
`f5`
  Flag 5
`f6`
  Flag 6
`f7`
  Flag 7
`s`
  Same as flag 4 (saturation flag)
`v`
  Same as flag 5 (overflow flag)
`va`
  Same as flag 6 (sticky overflow flag)
`c`
  Same as flag 7 (carry/borrow flag)
`b`
  Same as flag 7 (carry/borrow flag)

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#### 9.9.2.6 Addressing Modes

`as` understands the following addressing modes for the D30V. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct
`@Rn`
  Register indirect
`@Rn+`
  Register indirect with post-increment
`@Rn-`
  Register indirect with post-decrement
`@-SP`
  Register indirect with pre-decrement
`@(disp, Rn)`
  Register indirect with displacement
`addr`
  PC relative address (for branch or rep).
`#imm`
  Immediate data (the ``#'` is optional and ignored)

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### 9.9.3 Floating Point

The D30V has no hardware floating point, but the `.float` and `.double` directives generates IEEE floating-point numbers for compatibility with other development tools.

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### 9.9.4 Opcodes

For detailed information on the D30V machine instruction set, see D30V Architecture: A VLIW Microprocessor for Multimedia Applications (Mitsubishi Electric Corp.). `as` implements all the standard D30V opcodes. The only changes are those described in the section on size modifiers

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## 9.10 Epiphany Dependent Features

> 9.10.1 Options |  |
> 9.10.2 Epiphany Syntax |  |

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### 9.10.1 Options

`as` has two additional command-line options for the Epiphany architecture.

`-mepiphany`
  Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior.

`-mepiphany16`
  Restricts the permitted instructions to just the 16 bit set.

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### 9.10.2 Epiphany Syntax

> 9.10.2.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.10.2.1 Special Characters

The presence of a ``;'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ```'` character can be used to separate statements on the same line.

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## 9.11 H8/300 Dependent Features

> 9.11.1 Options |  |
> 9.11.2 Syntax |  |
> 9.11.3 Floating Point |  |
> 9.11.4 H8/300 Machine Directives |  |
> 9.11.5 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.11.1 Options

The Renesas H8/300 version of `as` has one machine-dependent option:

`-h-tick-hex`
  Support H'00 style hex constants in addition to 0x00 style.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.11.2 Syntax

> 9.11.2.1 Special Characters |  |
> 9.11.2.2 Register Names |  |
> 9.11.2.3 Addressing Modes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.11.2.1 Special Characters

``;'` is the line comment character.

``$'` can be used instead of a newline to separate statements. Therefore you may not use ``$'` in symbol names on the H8/300.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.11.2.2 Register Names

You can use predefined symbols of the form ``rnh'` and ``rnl'` to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from ``0'` to ``7'`); for instance, both ``r0h'` and ``r7l'` are valid register names.

You can also use the eight predefined symbols ``rn'` to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols ``ern'` (``er0'` ... ``er7'`) to refer to the 32-bit general purpose registers.

The two control registers are called `pc` (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and `ccr` (condition code register; an 8-bit register). `r7` is used as the stack pointer, and can also be called `sp`.

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#### 9.11.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

`rn`
  Register direct

`@rn`
  Register indirect

`@(d, rn)`
`@(d:16, rn)`
`@(d:24, rn)`
  Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)

`@rn+`
  Register indirect with post-increment

`@-rn`
  Register indirect with pre-decrement

``@`aa`
``@`aa:8`
``@`aa:16`
``@`aa:24`
  Absolute address `aa`. (The address size ``:24'` only makes sense on the H8/300H.)

`#xx`
`#xx:8`
`#xx:16`
`#xx:32`
  Immediate data xx. You may specify the ``:8'`, ``:16'`, or ``:32'` for clarity, if you wish; but `as` neither requires this nor uses it--the data size required is taken from context.

``@``@`aa`
``@``@`aa:8`
  Memory indirect. You may specify the ``:8'` for clarity, if you wish; but `as` neither requires this nor uses it.

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### 9.11.3 Floating Point

The H8/300 family has no hardware floating point, but the `.float` directive generates IEEE floating-point numbers for compatibility with other development tools.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.11.4 H8/300 Machine Directives

`as` has the following machine-dependent directives for the H8/300:

`.h8300h`
  Recognize and emit additional instructions for the H8/300H variant, and also make `.int` emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

`.h8300s`
  Recognize and emit additional instructions for the H8S variant, and also make `.int` emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

`.h8300hn`
  Recognize and emit additional instructions for the H8/300H variant in normal mode, and also make `.int` emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

`.h8300sn`
  Recognize and emit additional instructions for the H8S variant in normal mode, and also make `.int` emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) ``.word'` directives generate 16-bit numbers.

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### 9.11.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual. For information specific to the H8/300H, see H8/300H Series Programming Manual (Renesas).

`as` implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked ``*'` are opcodes used only on the H8/300H.

             Legend:
                Rs   source register
                Rd   destination register
                abs  absolute address
                imm  immediate data
             disp:N  N-bit displacement from a register
            pcrel:N  N-bit displacement relative to program counter

       add.b #imm,rd              *  andc #imm,ccr
       add.b rs,rd                   band #imm,rd
       add.w rs,rd                   band #imm,@rd
    *  add.w #imm,rd                 band #imm,@abs:8
    *  add.l rs,rd                   bra  pcrel:8
    *  add.l #imm,rd              *  bra  pcrel:16
       adds #imm,rd                  bt   pcrel:8
       addx #imm,rd               *  bt   pcrel:16
       addx rs,rd                    brn  pcrel:8
       and.b #imm,rd              *  brn  pcrel:16
       and.b rs,rd                   bf   pcrel:8
    *  and.w rs,rd                *  bf   pcrel:16
    *  and.w #imm,rd                 bhi  pcrel:8
    *  and.l #imm,rd              *  bhi  pcrel:16
    *  and.l rs,rd                   bls  pcrel:8
    *  bls  pcrel:16                 bld  #imm,rd
       bcc  pcrel:8                  bld  #imm,@rd
    *  bcc  pcrel:16                 bld  #imm,@abs:8
       bhs  pcrel:8                  bnot #imm,rd
    *  bhs  pcrel:16                 bnot #imm,@rd
       bcs  pcrel:8                  bnot #imm,@abs:8
    *  bcs  pcrel:16                 bnot rs,rd
       blo  pcrel:8                  bnot rs,@rd
    *  blo  pcrel:16                 bnot rs,@abs:8
       bne  pcrel:8                  bor  #imm,rd
    *  bne  pcrel:16                 bor  #imm,@rd
       beq  pcrel:8                  bor  #imm,@abs:8
    *  beq  pcrel:16                 bset #imm,rd
       bvc  pcrel:8                  bset #imm,@rd
    *  bvc  pcrel:16                 bset #imm,@abs:8
       bvs  pcrel:8                  bset rs,rd
    *  bvs  pcrel:16                 bset rs,@rd
       bpl  pcrel:8                  bset rs,@abs:8
    *  bpl  pcrel:16                 bsr  pcrel:8
       bmi  pcrel:8                  bsr  pcrel:16
    *  bmi  pcrel:16                 bst  #imm,rd
       bge  pcrel:8                  bst  #imm,@rd
    *  bge  pcrel:16                 bst  #imm,@abs:8
       blt  pcrel:8                  btst #imm,rd
    *  blt  pcrel:16                 btst #imm,@rd
       bgt  pcrel:8                  btst #imm,@abs:8
    *  bgt  pcrel:16                 btst rs,rd
       ble  pcrel:8                  btst rs,@rd
    *  ble  pcrel:16                 btst rs,@abs:8
       bclr #imm,rd                  bxor #imm,rd
       bclr #imm,@rd                 bxor #imm,@rd
       bclr #imm,@abs:8              bxor #imm,@abs:8
       bclr rs,rd                    cmp.b #imm,rd
       bclr rs,@rd                   cmp.b rs,rd
       bclr rs,@abs:8                cmp.w rs,rd
       biand #imm,rd                 cmp.w rs,rd
       biand #imm,@rd             *  cmp.w #imm,rd
       biand #imm,@abs:8          *  cmp.l #imm,rd
       bild #imm,rd               *  cmp.l rs,rd
       bild #imm,@rd                 daa  rs
       bild #imm,@abs:8              das  rs
       bior #imm,rd                  dec.b rs
       bior #imm,@rd              *  dec.w #imm,rd
       bior #imm,@abs:8           *  dec.l #imm,rd
       bist #imm,rd                  divxu.b rs,rd
       bist #imm,@rd              *  divxu.w rs,rd
       bist #imm,@abs:8           *  divxs.b rs,rd
       bixor #imm,rd              *  divxs.w rs,rd
       bixor #imm,@rd                eepmov
       bixor #imm,@abs:8          *  eepmovw
    *  exts.w rd                     mov.w rs,@abs:16
    *  exts.l rd                  *  mov.l #imm,rd
    *  extu.w rd                  *  mov.l rs,rd
    *  extu.l rd                  *  mov.l @rs,rd
       inc  rs                    *  mov.l @(disp:16,rs),rd
    *  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
    *  inc.l #imm,rd              *  mov.l @rs+,rd
       jmp  @rs                   *  mov.l @abs:16,rd
       jmp  abs                   *  mov.l @abs:24,rd
       jmp  @@abs:8               *  mov.l rs,@rd
       jsr  @rs                   *  mov.l rs,@(disp:16,rd)
       jsr  abs                   *  mov.l rs,@(disp:24,rd)
       jsr  @@abs:8               *  mov.l rs,@-rd
       ldc  #imm,ccr              *  mov.l rs,@abs:16
       ldc  rs,ccr                *  mov.l rs,@abs:24
    *  ldc  @abs:16,ccr              movfpe @abs:16,rd
    *  ldc  @abs:24,ccr              movtpe rs,@abs:16
    *  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
    *  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
    *  ldc  @rs+,ccr              *  mulxs.b rs,rd
    *  ldc  @rs,ccr               *  mulxs.w rs,rd
    *  mov.b @(disp:24,rs),rd        neg.b rs
    *  mov.b rs,@(disp:24,rd)     *  neg.w rs
       mov.b @abs:16,rd           *  neg.l rs
       mov.b rs,rd                   nop
       mov.b @abs:8,rd               not.b rs
       mov.b rs,@abs:8            *  not.w rs
       mov.b rs,rd                *  not.l rs
       mov.b #imm,rd                 or.b #imm,rd
       mov.b @rs,rd                  or.b rs,rd
       mov.b @(disp:16,rs),rd     *  or.w #imm,rd
       mov.b @rs+,rd              *  or.w rs,rd
       mov.b @abs:8,rd            *  or.l #imm,rd
       mov.b rs,@rd               *  or.l rs,rd
       mov.b rs,@(disp:16,rd)        orc  #imm,ccr
       mov.b rs,@-rd                 pop.w rs
       mov.b rs,@abs:8            *  pop.l rs
       mov.w rs,@rd                  push.w rs
    *  mov.w @(disp:24,rs),rd     *  push.l rs
    *  mov.w rs,@(disp:24,rd)        rotl.b rs
    *  mov.w @abs:24,rd           *  rotl.w rs
    *  mov.w rs,@abs:24           *  rotl.l rs
       mov.w rs,rd                   rotr.b rs
       mov.w #imm,rd              *  rotr.w rs
       mov.w @rs,rd               *  rotr.l rs
       mov.w @(disp:16,rs),rd        rotxl.b rs
       mov.w @rs+,rd              *  rotxl.w rs
       mov.w @abs:16,rd           *  rotxl.l rs
       mov.w rs,@(disp:16,rd)        rotxr.b rs
       mov.w rs,@-rd              *  rotxr.w rs
    *  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
       bpt                        *  stc  ccr,@-rd
       rte                        *  stc  ccr,@abs:16
       rts                        *  stc  ccr,@abs:24
       shal.b rs                     sub.b rs,rd
    *  shal.w rs                     sub.w rs,rd
    *  shal.l rs                  *  sub.w #imm,rd
       shar.b rs                  *  sub.l rs,rd
    *  shar.w rs                  *  sub.l #imm,rd
    *  shar.l rs                     subs #imm,rd
       shll.b rs                     subx #imm,rd
    *  shll.w rs                     subx rs,rd
    *  shll.l rs                  *  trapa #imm
       shlr.b rs                     xor  #imm,rd
    *  shlr.w rs                     xor  rs,rd
    *  shlr.l rs                  *  xor.w #imm,rd
       sleep                      *  xor.w rs,rd
       stc  ccr,rd                *  xor.l #imm,rd
    *  stc  ccr,@rs               *  xor.l rs,rd
    *  stc  ccr,@(disp:16,rd)        xorc #imm,ccr

Four H8/300 instructions (`add`, `cmp`, `mov`, `sub`) are defined with variants using the suffixes ``.b'`, ``.w'`, and ``.l'` to specify the size of a memory operand. `as` supports these suffixes, but does not require them; since one of the operands is always a register, `as` can deduce the correct size.

For example, since `r0` refers to a 16-bit register,

    mov    r0,@foo
    is equivalent to
    mov.w  r0,@foo

If you use the size suffixes, `as` issues a warning when the suffix and the register size do not match.

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## 9.12 HPPA Dependent Features

> 9.12.1 Notes |  |
> 9.12.2 Options |  |
> 9.12.3 Syntax |  |
> 9.12.4 Floating Point |  |
> 9.12.5 HPPA Assembler Directives |  | HPPA Machine Directives
> 9.12.6 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.12.1 Notes

As a back end for GNU CC `as` has been throughly tested and should work extremely well. We have tested it only minimally on hand written assembly code and no one has tested it much on the assembly output from the HP compilers.

The format of the debugging sections has changed since the original `as` port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA `as` port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

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### 9.12.2 Options

`as` has no machine-dependent command-line options for the HPPA.

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### 9.12.3 Syntax

The assembler syntax closely follows the HPPA instruction set reference manual; assembler directives and general syntax closely follow the HPPA assembly language reference manual, with a few noteworthy differences.

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the `spop` instructions, or code which makes significant use of the `!` line separator.

`as` is much less forgiving about missing arguments and other similar oversights than the HP assembler. `as` notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, `as` allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

``;'` is the line comment character.

``!'` can be used instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

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### 9.12.4 Floating Point

The HPPA family uses IEEE floating-point numbers.

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### 9.12.5 HPPA Assembler Directives

`as` for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

`as` does not support the following assembler directives described in the HP manual:

    .endm           .liston
    .enter          .locct
    .leave          .macro
    .listoff

Beyond those implemented for compatibility, `as` supports one additional assembler directive for the HPPA: `.param`. It conveys register argument locations for static functions. Its syntax closely follows the `.export` directive.

These are the additional directives in `as` for the HPPA:

`.block n`
`.blockz n`
  Reserve n bytes of storage, and initialize them to zero.

`.call`
  Mark the beginning of a procedure call. Only the special case with no arguments is allowed.

`.callinfo [ param=value, ... ] [ flag, ... ]`
  Specify a number of parameters and flags that define the environment for a procedure.

  param may be any of ``frame'` (frame size), ``entry_gr'` (end of general register range), ``entry_fr'` (end of float register range), ``entry_sr'` (end of space register range).

  The values for flag are ``calls'` or ``caller'` (proc has subroutines), ``no_calls'` (proc does not call subroutines), ``save_rp'` (preserve return pointer), ``save_sp'` (proc preserves stack pointer), ``no_unwind'` (do not unwind this proc), ``hpux_int'` (proc is interrupt routine).

`.code`
  Assemble into the standard section called ``$TEXT$'`, subsection ``$CODE$'`.

`.copyright "string"`
  In the SOM object format, insert string into the object code, marked as a copyright string.

`.copyright "string"`
  In the ELF object format, insert string into the object code, marked as a version string.

`.enter`
  Not yet supported; the assembler rejects programs containing this directive.

`.entry`
  Mark the beginning of a procedure.

`.exit`
  Mark the end of a procedure.

`.export name [ ,typ ] [ ,param=r ]`
  Make a procedure name available to callers. typ, if present, must be one of ``absolute'`, ``code'` (ELF only, not SOM), ``data'`, ``entry'`, ``data'`, ``entry'`, ``millicode'`, ``plabel'`, ``pri_prog'`, or ``sec_prog'`.

  param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be ``argwn'` (where n ranges from `0` to `3`, and indicates one of four one-word arguments); ``rtnval'` (the procedure's result); or ``priv_lev'` (privilege level). For arguments or the result, r specifies how to relocate, and must be one of ``no'` (not relocatable), ``gr'` (argument is in general register), ``fr'` (in floating point register), or ``fu'` (upper half of float register). For ``priv_lev'`, r is an integer.

`.half n`
  Define a two-byte integer constant n; synonym for the portable `as` directive `.short`.

`.import name [ ,typ ]`
  Converse of `.export`; make a procedure available to call. The arguments use the same conventions as the first two arguments for `.export`.

`.label name`
  Define name as a label for the current assembly location.

`.leave`
  Not yet supported; the assembler rejects programs containing this directive.

`.origin lc`
  Advance location counter to lc. Synonym for the `as` portable directive `.org`.

`.param name [ ,typ ] [ ,param=r ]`
  Similar to `.export`, but used for static procedures.

`.proc`
  Use preceding the first statement of a procedure.

`.procend`
  Use following the last statement of a procedure.

`label .reg expr`
  Synonym for `.equ`; define label with the absolute expression expr as its value.

`.space secname [ ,params ]`
  Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name.

  If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are ``spnum=exp'` (identify this section by the number exp, an absolute expression), ``sort=exp'` (order sections according to this sort key when linking; exp is an absolute expression), ``unloadable'` (section contains no loadable data), ``notdefined'` (this section defined elsewhere), and ``private'` (data in this section not available to other programs).

`.spnum secnam`
  Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA `.space` directive.)

`.string "str"`
  Copy the characters in the string str to the object file. See section Strings, for information on escape sequences you can use in `as` strings.

  Warning! The HPPA version of `.string` differs from the usual `as` definition: it does not write a zero byte after copying str.

`.stringz "str"`
  Like `.string`, but appends a zero byte after copying str to object file.

`.subspa name [ ,params ]`
`.nsubspa name [ ,params ]`
  Similar to `.space`, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of `.subspa` for this name).

  If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are ``quad=expr'` ("quadrant" for this subsection), ``align=expr'` (alignment for beginning of this subsection; a power of two), ``access=expr'` (value for "access rights" field), ``sort=expr'` (sorting order for this subspace in link), ``code_only'` (subsection contains only code), ``unloadable'` (subsection cannot be loaded into memory), ``comdat'` (subsection is comdat), ``common'` (subsection is common block), ``dup_comm'` (subsection may have duplicate names), or ``zero'` (subsection is all zeros, do not write in object file).

  `.nsubspa` always creates a new subspace with the given name, even if one with the same name already exists.

  ``comdat'`, ``common'` and ``dup_comm'` can be used to implement various flavors of one-only support when using the SOM linker. The SOM linker only supports specific combinations of these flags. The details are not documented. A brief description is provided here.

  ``comdat'` provides a form of linkonce support. It is useful for both code and data subspaces. A ``comdat'` subspace has a key symbol marked by the ``is_comdat'` flag or ``ST_COMDAT'`. Only the first subspace for any given key is selected. The key symbol becomes universal in shared links. This is similar to the behavior of ``secondary_def'` symbols.

  ``common'` provides Fortran named common support. It is only useful for data subspaces. Symbols with the flag ``is_common'` retain this flag in shared links. Referencing a ``is_common'` symbol in a shared library from outside the library doesn't work. Thus, ``is_common'` symbols must be output whenever they are needed.

  ``common'` and ``dup_comm'` together provide Cobol common support. The subspaces in this case must all be the same length. Otherwise, this support is similar to the Fortran common support.

  ``dup_comm'` by itself provides a type of one-only support for code. Only the first ``dup_comm'` subspace is selected. There is a rather complex algorithm to compare subspaces. Code symbols marked with the ``dup_common'` flag are hidden. This support was intended for "C++ duplicate inlines".

  A simplified technique is used to mark the flags of symbols based on the flags of their subspace. A symbol with the scope SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding settings of ``comdat'`, ``common'` and ``dup_comm'` from the subspace, respectively. This avoids having to introduce additional directives to mark these symbols. The HP assembler sets ``is_common'` from ``common'`. However, it doesn't set the ``dup_common'` from ``dup_comm'`. It doesn't have ``comdat'` support.

`.version "str"`
  Write str as version identifier in object code.

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### 9.12.6 Opcodes

For detailed information on the HPPA machine instruction set, see PA-RISC Architecture and Instruction Set Reference Manual (HP 09740-90039).

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## 9.13 ESA/390 Dependent Features

> 9.13.1 Notes |  |
> 9.13.2 Options |  |
> 9.13.3 Syntax |  |
> 9.13.4 Floating Point |  |
> 9.13.5 ESA/390 Assembler Directives |  | ESA/390 Machine Directives
> 9.13.6 Opcodes |  |

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### 9.13.1 Notes

The ESA/390 `as` port is currently intended to be a back-end for the GNU CC compiler. It is not HLASM compatible, although it does support a subset of some of the HLASM directives. The only supported binary file format is ELF; none of the usual MVS/VM/OE/USS object file formats, such as ESD or XSD, are supported.

When used with the GNU CC compiler, the ESA/390 `as` will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, dynamically loadable objects, and any relocation other than the 31-bit relocation.

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### 9.13.2 Options

`as` has no machine-dependent command-line options for the ESA/390.

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### 9.13.3 Syntax

The opcode/operand syntax follows the ESA/390 Principles of Operation manual; assembler directives and general syntax are loosely based on the prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives are not supported for the most part, with the exception of those described herein.

A leading dot in front of directives is optional, and the case of directives is ignored; thus for example, .using and USING have the same effect.

A colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

``#'` is the line comment character.

``;'` can be used instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using thesse symbolic names, `as` can detect simple syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4.

``*'` is the current location counter. Unlike ``.'` it is always relative to the last USING directive. Note that this means that expressions cannot use multiplication, as any occurrence of ``*'` will be interpreted as a location counter.

All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement.

Many of the usual forms of address constants / address literals are supported. Thus,

    	.using	*,r3
    	L	r15,=A(some_routine)
    	LM	r6,r7,=V(some_longlong_extern)
    	A	r1,=F'12'
    	AH	r0,=H'42'
    	ME	r6,=E'3.1416'
    	MD	r6,=D'3.14159265358979'
    	O	r6,=XL4'cacad0d0'
    	.ltorg

should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the `.using` directive).

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### 9.13.4 Floating Point

The assembler generates only IEEE floating-point numbers. The older floating point formats are not supported.

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### 9.13.5 ESA/390 Assembler Directives

`as` for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are `.using` and `.ltorg`

These are the additional directives in `as` for the ESA/390:

`.dc`
  A small subset of the usual DC directive is supported.

`.drop regno`
  Stop using regno as the base register. The regno must have been previously declared with a `.using` directive in the same section as the current section.

`.ebcdic string`
  Emit the EBCDIC equivalent of the indicated string. The emitted string will be null terminated. Note that the directives `.string` etc. emit ascii strings by default.

`EQU`
  The standard HLASM-style EQU directive is not supported; however, the standard `as` directive .equ can be used to the same effect.

`.ltorg`
  Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order to generate correct assembly, a `.using` must have been previously specified in the same section.

`.using expr,regno`
  Use regno as the base register for all subsequent RX, RS, and SS form instructions. The expr will be evaluated to obtain the base address; usually, expr will merely be ``*'`.

  This assembler allows two `.using` directives to be simultaneously outstanding, one in the `.text` section, and one in another section (typically, the `.data` section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward way. A `.using` directive must always be specified in the `.text` section; this will specify the base register that will be used for branches in the `.text` section. A second `.using` may be specified in another section; this will specify the base register that is used for non-label address literals. When a second `.using` is specified, then the subsequent `.ltorg` must be put in the same section; otherwise an error will result.

  Thus, for example, the following code uses `r3` to address branch targets and `r4` to address the literal pool, which has been written to the `.data` section. The is, the constants `=A(some_routine)`, `=H'42'` and `=E'3.1416'` will all appear in the `.data` section.

      .data
      	.using  LITPOOL,r4
      .text
      	BASR	r3,0
      	.using	*,r3
              B       START
      	.long	LITPOOL
      START:
      	L	r4,4(,r3)
      	L	r15,=A(some_routine)
      	LTR	r15,r15
      	BNE	LABEL
      	AH	r0,=H'42'
      LABEL:
      	ME	r6,=E'3.1416'
      .data
      LITPOOL:
      	.ltorg

  Note that this dual-`.using` directive semantics extends and is not compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics.

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### 9.13.6 Opcodes

For detailed information on the ESA/390 machine instruction set, see ESA/390 Principles of Operation (IBM Publication Number DZ9AR004).

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## 9.14 80386 Dependent Features

The i386 version `as` supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

> 9.14.1 Options |  |
> 9.14.2 x86 specific Directives |  | X86 specific directives
> 9.14.3 i386 Syntactical Considerations |  | Syntactical considerations
> 9.14.4 Instruction Naming |  |
> 9.14.6 Register Naming |  |
> 9.14.7 Instruction Prefixes |  |
> 9.14.8 Memory References |  |
> 9.14.9 Handling of Jump Instructions |  |
> 9.14.10 Floating Point |  |
> 9.14.11 Intel's MMX and AMD's 3DNow! SIMD Operations |  |
> 9.14.12 AMD's Lightweight Profiling Instructions |  |
> 9.14.13 Bit Manipulation Instructions |  | Bit Manipulation Instruction
> 9.14.14 AMD's Trailing Bit Manipulation Instructions |  |
> 9.14.15 Writing 16-bit Code |  |
> 9.14.17 Specifying CPU Architecture |  | Specifying an x86 CPU architecture
> 9.14.16 AT&T Syntax bugs |  |
> 9.14.18 Notes |  |

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### 9.14.1 Options

The i386 version of `as` has a few machine dependent options:

`--32 | --x32 | --64`
  Select the word size, either 32 bits or 64 bits. ``--32'` implies Intel i386 architecture, while ``--x32'` and ``--64'` imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively.

  These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

`-n`
  By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization.

`--divide`
  On SVR4-derived platforms, the character ``/'` is treated as a comment character, which means that it cannot be used in expressions. The ``--divide'` option turns ``/'` into a normal character. This does not disable ``/'` at the beginning of a line starting a comment, or affect using ``#'` for starting a comment.

`-march=CPU[+EXTENSION...]`
  This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: `i8086`, `i186`, `i286`, `i386`, `i486`, `i586`, `i686`, `pentium`, `pentiumpro`, `pentiumii`, `pentiumiii`, `pentium4`, `prescott`, `nocona`, `core`, `core2`, `corei7`, `l1om`, `k1om`, `k6`, `k6_2`, `athlon`, `opteron`, `k8`, `amdfam10`, `bdver1`, `bdver2`, `bdver3`, `bdver4`, `btver1`, `btver2`, `generic32` and `generic64`.

  In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, `-march=i686+sse4+vmx` extends i686 with sse4 and vmx. The following extensions are currently supported: `8087`, `287`, `387`, `no87`, `mmx`, `nommx`, `sse`, `sse2`, `sse3`, `ssse3`, `sse4.1`, `sse4.2`, `sse4`, `nosse`, `avx`, `avx2`, `adx`, `rdseed`, `prfchw`, `smap`, `mpx`, `sha`, `avx512f`, `avx512cd`, `avx512er`, `avx512pf`, `noavx`, `vmx`, `vmfunc`, `smx`, `xsave`, `xsaveopt`, `aes`, `pclmul`, `fsgsbase`, `rdrnd`, `f16c`, `bmi2`, `fma`, `movbe`, `ept`, `lzcnt`, `hle`, `rtm`, `invpcid`, `clflush`, `lwp`, `fma4`, `xop`, `cx16`, `syscall`, `rdtscp`, `3dnow`, `3dnowa`, `sse4a`, `sse5`, `svme`, `abm` and `padlock`. Note that rather than extending a basic instruction set, the extension mnemonics starting with `no` revoke the respective functionality.

  When the `.arch` directive is used with ``-march'`, the `.arch` directive will take precedent.

`-mtune=CPU`
  This option specifies a processor to optimize for. When used in conjunction with the ``-march'` option, only instructions of the processor specified by the ``-march'` option will be generated.

  Valid CPU values are identical to the processor list of ``-march=CPU'`.

`-msse2avx`
  This option specifies that the assembler should encode SSE instructions with VEX prefix.

`-msse-check=none`
`-msse-check=warning`
`-msse-check=error`
  These options control if the assembler should check SSE instructions. ``-msse-check=none'` will make the assembler not to check SSE instructions, which is the default. ``-msse-check=warning'` will make the assembler issue a warning for any SSE instruction. ``-msse-check=error'` will make the assembler issue an error for any SSE instruction.

`-mavxscalar=128`
`-mavxscalar=256`
  These options control how the assembler should encode scalar AVX instructions. ``-mavxscalar=128'` will encode scalar AVX instructions with 128bit vector length, which is the default. ``-mavxscalar=256'` will encode scalar AVX instructions with 256bit vector length.

`-mevexlig=128`
`-mevexlig=256`
`-mevexlig=512`
  These options control how the assembler should encode length-ignored (LIG) EVEX instructions. ``-mevexlig=128'` will encode LIG EVEX instructions with 128bit vector length, which is the default. ``-mevexlig=256'` and ``-mevexlig=512'` will encode LIG EVEX instructions with 256bit and 512bit vector length, respectively.

`-mevexwig=0`
`-mevexwig=1`
  These options control how the assembler should encode w-ignored (WIG) EVEX instructions. ``-mevexwig=0'` will encode WIG EVEX instructions with evex.w = 0, which is the default. ``-mevexwig=1'` will encode WIG EVEX instructions with evex.w = 1.

`-mmnemonic=att`
`-mmnemonic=intel`
  This option specifies instruction mnemonic for matching instructions. The `.att_mnemonic` and `.intel_mnemonic` directives will take precedent.

`-msyntax=att`
`-msyntax=intel`
  This option specifies instruction syntax when processing instructions. The `.att_syntax` and `.intel_syntax` directives will take precedent.

`-mnaked-reg`
  This opetion specifies that registers don't require a ``%'` prefix. The `.att_syntax` and `.intel_syntax` directives will take precedent.

`-madd-bnd-prefix`
  This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code.

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### 9.14.2 x86 specific Directives

`.lcomm symbol , length[, alignment]`
  Reserve length (an absolute expression) bytes for a local common denoted by symbol. The section and value of symbol are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. Since symbol is not declared global, it is normally not visible to `ld`. The optional third parameter, alignment, specifies the desired alignment of the symbol in the bss section.

  This directive is only available for COFF based x86 targets.

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### 9.14.3 i386 Syntactical Considerations

> 9.14.3.1 AT&T Syntax versus Intel Syntax |  |
> 9.14.3.2 Special Characters |  |

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#### 9.14.3.1 AT&T Syntax versus Intel Syntax

`as` now supports assembly using Intel assembler syntax. `.intel_syntax` selects Intel mode, and `.att_syntax` switches back to the usual AT&T mode for compatibility with the output of `gcc`. Either of these directives may have an optional argument, `prefix`, or `noprefix` specifying whether registers require a ``%'` prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

- AT&T immediate operands are preceded by ``$'`; Intel immediate operands are undelimited (Intel ``push 4'` is AT&T ``pushl $4'`). AT&T register operands are preceded by ``%'`; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by ``*'`; they are undelimited in Intel syntax.

- AT&T and Intel syntax use the opposite order for source and destination operands. Intel ``add eax, 4'` is ``addl $4, %eax'`. The ``source, dest'` convention is maintained for compatibility with previous Unix assemblers. Note that ``bound'`, ``invlpga'`, and instructions with 2 immediate operands, such as the ``enter'` instruction, do not have reversed order. 9.14.16 AT&T Syntax bugs.

- In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of ``b'`, ``w'`, ``l'` and ``q'` specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with ``byte ptr'`, ``word ptr'`, ``dword ptr'` and ``qword ptr'`. Thus, Intel ``mov al, byte ptr foo'` is ``movb foo, %al'` in AT&T syntax.

  In 64-bit code, ``movabs'` can be used to encode the ``mov'` instruction with the 64-bit displacement or immediate operand.

- Immediate form long jumps and calls are ``lcall/ljmp $section, $offset'` in AT&T syntax; the Intel syntax is ``call/jmp far section:offset'`. Also, the far return instruction is ``lret $stack-adjust'` in AT&T syntax; Intel syntax is ``ret far stack-adjust'`.

- The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

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#### 9.14.3.2 Special Characters

The presence of a ``#'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

If the ``--divide'` command line option has not been specified then the ``/'` character appearing anywhere on a line also introduces a line comment.

The ``;'` character can be used to separate statements on the same line.

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### 9.14.4 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters ``b'`, ``w'`, ``l'` and ``q'` specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then `as` tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, ``mov %ax, %bx'` is equivalent to ``movw %ax, %bx'`; also, ``mov $1, %bx'` is equivalent to ``movw $1, bx'`. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are ``movs...'` and ``movz...'` in AT&T syntax (``movsx'` and ``movzx'` in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, ``movsbl %al, %edx'` is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are ``bl'` (from byte to long), ``bw'` (from byte to word), ``wl'` (from word to long), ``bq'` (from byte to quadruple word), ``wq'` (from word to quadruple word), and ``lq'` (from long to quadruple word).

Different encoding options can be specified via optional mnemonic suffix. ``.s'` suffix swaps 2 register operands in encoding when moving from one register to another. ``.d8'` or ``.d32'` suffix prefers 8bit or 32bit displacement in encoding.

The Intel-syntax conversion instructions

- ``cbw'` -- sign-extend byte in ``%al'` to word in ``%ax'`,

- ``cwde'` -- sign-extend word in ``%ax'` to long in ``%eax'`,

- ``cwd'` -- sign-extend word in ``%ax'` to long in ``%dx:%ax'`,

- ``cdq'` -- sign-extend dword in ``%eax'` to quad in ``%edx:%eax'`,

- ``cdqe'` -- sign-extend dword in ``%eax'` to quad in ``%rax'` (x86-64 only),

- ``cqo'` -- sign-extend quad in ``%rax'` to octuple in ``%rdx:%rax'` (x86-64 only),

are called ``cbtw'`, ``cwtl'`, ``cwtd'`, ``cltd'`, ``cltq'`, and ``cqto'` in AT&T naming. `as` accepts either naming for these instructions.

Far call/jump instructions are ``lcall'` and ``ljmp'` in AT&T syntax, but are ``call far'` and ``jump far'` in Intel convention.

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### 9.14.5 AT&T Mnemonic versus Intel Mnemonic

`as` supports assembly using Intel mnemonic. `.intel_mnemonic` selects Intel mnemonic with Intel syntax, and `.att_mnemonic` switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the output of `gcc`. Several x87 instructions, ``fadd'`, ``fdiv'`, ``fdivp'`, ``fdivr'`, ``fdivrp'`, ``fmul'`, ``fsub'`, ``fsubp'`, ``fsubr'` and ``fsubrp'`, are implemented in AT&T System V/386 assembler with different mnemonics from those in Intel IA32 specification. `gcc` generates those instructions with AT&T mnemonic.

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### 9.14.6 Register Naming

Register operands are always prefixed with ``%'`. The 80386 registers consist of

- the 8 32-bit registers ``%eax'` (the accumulator), ``%ebx'`, ``%ecx'`, ``%edx'`, ``%edi'`, ``%esi'`, ``%ebp'` (the frame pointer), and ``%esp'` (the stack pointer).

- the 8 16-bit low-ends of these: ``%ax'`, ``%bx'`, ``%cx'`, ``%dx'`, ``%di'`, ``%si'`, ``%bp'`, and ``%sp'`.

- the 8 8-bit registers: ``%ah'`, ``%al'`, ``%bh'`, ``%bl'`, ``%ch'`, ``%cl'`, ``%dh'`, and ``%dl'` (These are the high-bytes and low-bytes of ``%ax'`, ``%bx'`, ``%cx'`, and ``%dx'`)

- the 6 section registers ``%cs'` (code section), ``%ds'` (data section), ``%ss'` (stack section), ``%es'`, ``%fs'`, and ``%gs'`.

- the 3 processor control registers ``%cr0'`, ``%cr2'`, and ``%cr3'`.

- the 6 debug registers ``%db0'`, ``%db1'`, ``%db2'`, ``%db3'`, ``%db6'`, and ``%db7'`.

- the 2 test registers ``%tr6'` and ``%tr7'`.

- the 8 floating point register stack ``%st'` or equivalently ``%st(0)'`, ``%st(1)'`, ``%st(2)'`, ``%st(3)'`, ``%st(4)'`, ``%st(5)'`, ``%st(6)'`, and ``%st(7)'`. These registers are overloaded by 8 MMX registers ``%mm0'`, ``%mm1'`, ``%mm2'`, ``%mm3'`, ``%mm4'`, ``%mm5'`, ``%mm6'` and ``%mm7'`.

- the 8 SSE registers registers ``%xmm0'`, ``%xmm1'`, ``%xmm2'`, ``%xmm3'`, ``%xmm4'`, ``%xmm5'`, ``%xmm6'` and ``%xmm7'`.

The AMD x86-64 architecture extends the register set by:

- enhancing the 8 32-bit registers to 64-bit: ``%rax'` (the accumulator), ``%rbx'`, ``%rcx'`, ``%rdx'`, ``%rdi'`, ``%rsi'`, ``%rbp'` (the frame pointer), ``%rsp'` (the stack pointer)

- the 8 extended registers ``%r8'`--``%r15'`.

- the 8 32-bit low ends of the extended registers: ``%r8d'`--``%r15d'`

- the 8 16-bit low ends of the extended registers: ``%r8w'`--``%r15w'`

- the 8 8-bit low ends of the extended registers: ``%r8b'`--``%r15b'`

- the 4 8-bit registers: ``%sil'`, ``%dil'`, ``%bpl'`, ``%spl'`.

- the 8 debug registers: ``%db8'`--``%db15'`.

- the 8 SSE registers: ``%xmm8'`--``%xmm15'`.

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### 9.14.7 Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the ``scas'` (scan string) instruction is repeated with:

            repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that `as` does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

- Section override prefixes ``cs'`, ``ds'`, ``ss'`, ``es'`, ``fs'`, ``gs'`. These are automatically added by specifying using the section:memory-operand form for memory references.

- Operand/Address size prefixes ``data16'` and ``addr16'` change 32-bit operands/addresses into 16-bit operands/addresses, while ``data32'` and ``addr32'` change 16-bit ones (in a `.code16` section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit `.code16` section, you might write:

              addr32 jmpl *(%ebx)

- The bus lock prefix ``lock'` inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).

- The wait for coprocessor prefix ``wait'` waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.

- The ``rep'`, ``repe'`, and ``repne'` prefixes are added to string instructions to make them repeat ``%ecx'` times (``%cx'` times if the current address size is 16-bits).
- The ``rex'` family of prefixes is used by x86-64 to encode extensions to i386 instruction set. The ``rex'` prefix has four bits -- an operand size overwrite (`64`) used to change operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the register set.

  You may write the ``rex'` prefixes directly. The ``rex64xyz'` instruction emits ``rex'` prefix with all the bits set. By omitting the `64`, `x`, `y` or `z` you may write other prefixes as well. Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands.

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### 9.14.8 Memory References

An Intel syntax indirect memory reference of the form

    section:[base + index*scale + disp]

is translated into the AT&T syntax

    section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a ``%'`. If you specify a section override which coincides with the default section register, `as` does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: ``-4(%ebp)'`, Intel: ``[ebp - 4]'`
  base is ``%ebp'`; disp is ``-4'`. section is missing, and the default section is used (``%ss'` for addressing with ``%ebp'` as the base register). index, scale are both missing.

AT&T: ``foo(,%eax,4)'`, Intel: ``[foo + eax*4]'`
  index is ``%eax'` (scaled by a scale 4); disp is ``foo'`. All other fields are missing. The section register here defaults to ``%ds'`.

AT&T: ``foo(,1)'`; Intel ``[foo]'`
  This uses the value pointed to by ``foo'` as a memory operand. Note that base and index are both missing, but there is only one ``,'`. This is a syntactic exception.

AT&T: ``%gs:foo'`; Intel ``gs:foo'`
  This selects the contents of the variable ``foo'` with section register section being ``%gs'`.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with ``*'`. If no ``*'` is specified, `as` always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (``b'`, ``w'`, ``l'` or ``q'`, respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using ``rip'` as a base register. Only constant offsets are valid. For example:

AT&T: ``1234(%rip)'`, Intel: ``[rip + 1234]'`
  Points to the address 1234 bytes past the end of the current instruction.

AT&T: ``symbol(%rip)'`, Intel: ``[rip + symbol]'`
  Points to the `symbol` in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

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### 9.14.9 Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the ``data16'` instruction prefix), since the 80386 insists upon masking ``%eip'` to 16 bits after the word displacement is added. (See also see section 9.14.17 Specifying CPU Architecture)

Note that the ``jcxz'`, ``jecxz'`, ``loop'`, ``loopz'`, ``loope'`, ``loopnz'` and ``loopne'` instructions only come in byte displacements, so that if you use these instructions (`gcc` does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding ``jcxz foo'` to

             jcxz cx_zero
             jmp cx_nonzero
    cx_zero: jmp foo
    cx_nonzero:

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### 9.14.10 Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

- Floating point constructors are ``.float'` or ``.single'`, ``.double'`, and ``.tfloat'` for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes ``s'`, ``l'`, and ``t'`. ``t'` stands for 80-bit (ten byte) real. The 80387 only supports this format via the ``fldt'` (load 80-bit real to stack top) and ``fstpt'` (store 80-bit real and pop stack) instructions.

- Integer constructors are ``.word'`, ``.long'` or ``.int'`, and ``.quad'` for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are ``s'` (single), ``l'` (long), and ``q'` (quad). As with the 80-bit real format, the 64-bit ``q'` format is only present in the ``fildq'` (load quad integer to stack top) and ``fistpq'` (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. ``fstl %st, %st(1)'` will give a warning, and be assembled as if you wrote ``fst %st, %st(1)'`, since all register to register operations use 80-bit floating point operands. (Contrast this with ``fstl %st, mem'`, which converts ``%st'` from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location ``mem'`)

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### 9.14.11 Intel's MMX and AMD's 3DNow! SIMD Operations

`as` supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, `as` does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called ``%mm0'`, ``%mm1'`, ... ``%mm7'`. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

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### 9.14.12 AMD's Lightweight Profiling Instructions

`as` supports AMD's Lightweight Profiling (LWP) instruction set, available on AMD's Family 15h (Orochi) processors.

LWP enables applications to collect and manage performance data, and react to performance events. The collection of performance data requires no context switches. LWP runs in the context of a thread and so several counters can be used independently across multiple threads. LWP can be used in both 64-bit and legacy 32-bit modes.

For detailed information on the LWP instruction set, see the AMD Lightweight Profiling Specification available at Lightweight Profiling Specification.

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### 9.14.13 Bit Manipulation Instructions

`as` supports the Bit Manipulation (BMI) instruction set.

BMI instructions provide several instructions implementing individual bit manipulation operations such as isolation, masking, setting, or resetting.

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### 9.14.14 AMD's Trailing Bit Manipulation Instructions

`as` supports AMD's Trailing Bit Manipulation (TBM) instruction set, available on AMD's BDVER2 processors (Trinity and Viperfish).

TBM instructions provide instructions implementing individual bit manipulation operations such as isolating, masking, setting, resetting, complementing, and operations on trailing zeros and ones.

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### 9.14.15 Writing 16-bit Code

While `as` normally writes only "pure" 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a ``.code16'` or ``.code16gcc'` directive before the assembly language instructions to be run in 16-bit mode. You can switch `as` to writing 32-bit code with the ``.code32'` directive or 64-bit code with the ``.code64'` directive.

``.code16gcc'` provides experimental support for generating 16-bit code from gcc, and differs from ``.code16'` in that ``call'`, ``ret'`, ``enter'`, ``leave'`, ``push'`, ``pop'`, ``pusha'`, ``popa'`, ``pushf'`, and ``popf'` instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. ``.code16gcc'` also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which `as` generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require `as` to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes ``66 6a 04'`, which pushes the value ``4'` onto the stack, decrementing ``%esp'` by 2.

            pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes ``6a 04'` (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

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### 9.14.16 AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

            fsub %st,%st(3)

results in ``%st(3)'` being updated to ``%st - %st(3)'` rather than the expected ``%st(3) - %st'`. This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is ``%st'` and the destination register is ``%st(i)'`.

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### 9.14.17 Specifying CPU Architecture

`as` may be told to assemble for a particular CPU (sub-)architecture with the `.arch cpu_type` directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

``i8086'` | ``i186'` | ``i286'` | ``i386'`
``i486'` | ``i586'` | ``i686'` | ``pentium'`
``pentiumpro'` | ``pentiumii'` | ``pentiumiii'` | ``pentium4'`
``prescott'` | ``nocona'` | ``core'` | ``core2'`
``corei7'` | ``l1om'` | ``k1om'`
``k6'` | ``k6_2'` | ``athlon'` | ``k8'`
``amdfam10'` | ``bdver1'` | ``bdver2'` | ``bdver3'`
``bdver4'` | ``btver1'` | ``btver2'`
``generic32'` | ``generic64'`
``.mmx'` | ``.sse'` | ``.sse2'` | ``.sse3'`
``.ssse3'` | ``.sse4.1'` | ``.sse4.2'` | ``.sse4'`
``.avx'` | ``.vmx'` | ``.smx'` | ``.ept'`
``.clflush'` | ``.movbe'` | ``.xsave'` | ``.xsaveopt'`
``.aes'` | ``.pclmul'` | ``.fma'` | ``.fsgsbase'`
``.rdrnd'` | ``.f16c'` | ``.avx2'` | ``.bmi2'`
``.lzcnt'` | ``.invpcid'` | ``.vmfunc'` | ``.hle'`
``.rtm'` | ``.adx'` | ``.rdseed'` | ``.prfchw'`
``.smap'` | ``.mpx'`
``.smap'` | ``.sha'`
``.3dnow'` | ``.3dnowa'` | ``.sse4a'` | ``.sse5'`
``.syscall'` | ``.rdtscp'` | ``.svme'` | ``.abm'`
``.lwp'` | ``.fma4'` | ``.xop'` | ``.cx16'`
``.padlock'`
``.smap'` | ``.avx512f'` | ``.avx512cd'` | ``.avx512er'`
``.avx512pf'` | ``.3dnow'` | ``.3dnowa'` | ``.sse4a'`
``.sse5'` | ``.syscall'` | ``.rdtscp'` | ``.svme'`
``.abm'` | ``.lwp'` | ``.fma4'` | ``.xop'`
``.cx16'` | ``.padlock'`

Apart from the warning, there are only two other effects on `as` operation; Firstly, if you specify a CPU other than ``i486'`, then shift by one instructions such as ``sarl $1, %eax'` will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing ``sarl %eax'`. Secondly, if you specify ``i8086'`, ``i186'`, or ``i286'`, and ``.code16'` or ``.code16gcc'` then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture (but not a sub-architecture, which are those starting with a dot), you may specify ``jumps'` or ``nojumps'` to control automatic promotion of conditional jumps. ``jumps'` is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see section 9.14.9 Handling of Jump Instructions) ``nojumps'` leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that `as` promotes. Unconditional jumps are treated as for ``jumps'`.

For example

     .arch i8086,nojumps

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### 9.14.18 Notes

There is some trickery concerning the ``mul'` and ``imul'` instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode ``0xf6'`; extension 4 for ``mul'` and 5 for ``imul'`) can be output only in the one operand form. Thus, ``imul %ebx, %eax'` does not select the expanding multiply; the expanding multiply would clobber the ``%edx'` register, and this would confuse `gcc` output. Use ``imul %ebx'` to get the 64-bit product in ``%edx:%eax'`.

We have added a two operand form of ``imul'` when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying ``%eax'` by 69, for example, can be done with ``imul $69, %eax'` rather than ``imul $69, %eax, %eax'`.

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## 9.15 Intel i860 Dependent Features

> 9.15.1 i860 Notes |  |
> 9.15.2 i860 Command-line Options |  |
> 9.15.3 i860 Machine Directives |  |
> 9.15.4 i860 Opcodes |  |
> 9.15.5 i860 Syntax |  |

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### 9.15.1 i860 Notes

This is a fairly complete i860 assembler which is compatible with the UNIX System V/860 Release 4 assembler. However, it does not currently support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT`).

Like the SVR4/860 assembler, the output object format is ELF32. Currently, this is the only supported object format. If there is sufficient interest, other formats such as COFF may be implemented.

Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter being the default. One difference is that AT&T syntax requires the '%' prefix on register names while Intel syntax does not. Another difference is in the specification of relocatable expressions. The Intel syntax is `ha%expression` whereas the SVR4 syntax is `[expression]@ha` (and similarly for the "l" and "h" selectors).

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### 9.15.2 i860 Command-line Options

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#### 9.15.2.1 SVR4 compatibility options

`-V`
  Print assembler version.
`-Qy`
  Ignored.
`-Qn`
  Ignored.

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#### 9.15.2.2 Other options

`-EL`
  Select little endian output (this is the default).
`-EB`
  Select big endian output. Note that the i860 always reads instructions as little endian data, so this option only effects data and not instructions.
`-mwarn-expand`
  Emit a warning message if any pseudo-instruction expansions occurred. For example, a `or` instruction with an immediate larger than 16-bits will be expanded into two instructions. This is a very undesirable feature to rely on, so this flag can help detect any code where it happens. One use of it, for instance, has been to find and eliminate any place where `gcc` may emit these pseudo-instructions.
`-mxp`
  Enable support for the i860XP instructions and control registers. By default, this option is disabled so that only the base instruction set (i.e., i860XR) is supported.
`-mintel-syntax`
  The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the Intel syntax.

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### 9.15.3 i860 Machine Directives

`.dual`
  Enter dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the `d.` prefix.

`.enddual`
  Exit dual instruction mode. While this directive is supported, the preferred way to use dual instruction mode is to explicitly code the dual bit with the `d.` prefix.

`.atmp`
  Change the temporary register used when expanding pseudo operations. The default register is `r31`.

The `.dual`, `.enddual`, and `.atmp` directives are available only in the Intel syntax mode.

Both syntaxes allow for the standard `.align` directive. However, the Intel syntax additionally allows keywords for the alignment parameter: "`.align type`", where `type' is one of `.short`, `.long`, `.quad`, `.single`, `.double` representing alignments of 2, 4, 16, 4, and 8, respectively.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.15.4 i860 Opcodes

All of the Intel i860XR and i860XP machine instructions are supported. Please see either i860 Microprocessor Programmer's Reference Manual or i860 Microprocessor Architecture for more information.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.15.4.1 Other instruction support (pseudo-instructions)

For compatibility with some other i860 assemblers, a number of pseudo-instructions are supported. While these are supported, they are a very undesirable feature that should be avoided -- in particular, when they result in an expansion to multiple actual i860 instructions. Below are the pseudo-instructions that result in expansions.

- Load large immediate into general register:

  The pseudo-instruction `mov imm,%rn` (where the immediate does not fit within a signed 16-bit field) will be expanded into:

      orh large_imm@h,%r0,%rn
      or large_imm@l,%rn,%rn

- Load/store with relocatable address expression:

  For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn` will be expanded into:

      orh addr_exp@ha,%rx,%r31
      ld.l addr_exp@l(%r31),%rn

  The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, fst.x`, and `pst.x` as well.

- Signed large immediate with add/subtract:

  If any of the arithmetic operations `adds, addu, subs, subu` are used with an immediate larger than 16-bits (signed), then they will be expanded. For instance, the pseudo-instruction `adds large_imm,%rx,%rn` expands to:

      orh large_imm@h,%r0,%r31
      or large_imm@l,%r31,%r31
      adds %r31,%rx,%rn

- Unsigned large immediate with logical operations:

  Logical operations (`or, andnot, or, xor`) also result in expansions. The pseudo-instruction `or large_imm,%rx,%rn` results in:

      orh large_imm@h,%rx,%r31
      or large_imm@l,%r31,%rn

  Similarly for the others, except for `and` which expands to:

      andnot (-1 - large_imm)@h,%rx,%r31
      andnot (-1 - large_imm)@l,%r31,%rn

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### 9.15.5 i860 Syntax

> 9.15.5.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.15.5.1 Special Characters

The presence of a ``#'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.16 Intel 80960 Dependent Features

> 9.16.1 i960 Command-line Options |  |
> 9.16.2 Floating Point |  |
> 9.16.3 i960 Machine Directives |  |
> 9.16.4 i960 Opcodes |  |
> 9.16.5 Syntax for the i960 |  | i960 Syntax

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.16.1 i960 Command-line Options

`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC`
  Select the 80960 architecture. Instructions or features not supported by the selected architecture cause fatal errors.

  ``-ACA'` is equivalent to ``-ACA_A'`; ``-AKC'` is equivalent to ``-AMC'`. Synonyms are provided for compatibility with other tools.

  If you do not specify any of these options, `as` generates code for any instruction or feature that is supported by some version of the 960 (even if this means mixing architectures!). In principle, `as` attempts to deduce the minimal sufficient processor type if none is specified; depending on the object code format, the processor type may be recorded in the object file. If it is critical that the `as` output match a specific architecture, specify that architecture explicitly.

`-b`
  Add code to collect information about conditional branches taken, for later optimization using branch prediction bits. (The conditional branch instructions have branch prediction bits in the CA, CB, and CC architectures.) If BR represents a conditional branch instruction, the following represents the code generated by the assembler when ``-b'` is specified:

              call    increment routine
              .word   0       # pre-counter
      Label:  BR
              call    increment routine
              .word   0       # post-counter

  The counter following a branch records the number of times that branch was not taken; the difference between the two counters is the number of times the branch was taken.

  A table of every such `Label` is also generated, so that the external postprocessor `gbr960` (supplied by Intel) can locate all the counters. This table is always labeled ``__BRANCH_TABLE__'`; this is a local symbol to permit collecting statistics for many separate object files. The table is word aligned, and begins with a two-word header. The first word, initialized to 0, is used in maintaining linked lists of branch tables. The second word is a count of the number of entries in the table, which follow immediately: each is a word, pointing to one of the labels illustrated above.

       +------------+------------+------------+ ... +------------+
       |            |            |            |     |            |
       |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
       |            |            |            |     |            |
       +------------+------------+------------+ ... +------------+

                     __BRANCH_TABLE__ layout

  The first word of the header is used to locate multiple branch tables, since each object file may contain one. Normally the links are maintained with a call to an initialization routine, placed at the beginning of each function in the file. The GNU C compiler generates these calls automatically when you give it a ``-b'` option. For further details, see the documentation of ``gbr960'`.

`-no-relax`
  Normally, Compare-and-Branch instructions with targets that require displacements greater than 13 bits (or that have external targets) are replaced with the corresponding compare (or ``chkbit'`) and branch instructions. You can use the ``-no-relax'` option to specify that `as` should generate errors instead, if the target displacement is larger than 13 bits.

  This option does not affect the Compare-and-Jump instructions; the code emitted for them is always adjusted when necessary (depending on displacement size), regardless of whether you use ``-no-relax'`.

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### 9.16.2 Floating Point

`as` generates IEEE floating-point numbers for the directives ``.float'`, ``.double'`, ``.extended'`, and ``.single'`.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.16.3 i960 Machine Directives

`.bss symbol, length, align`
  Reserve length bytes in the bss section for a local symbol, aligned to the power of two specified by align. length and align must be positive absolute expressions. This directive differs from ``.lcomm'` only in that it permits you to specify an alignment. See section `.lcomm`.

`.extended flonums`
  `.extended` expects zero or more flonums, separated by commas; for each flonum, ``.extended'` emits an IEEE extended-format (80-bit) floating-point number.

`.leafproc call-lab, bal-lab`
  You can use the ``.leafproc'` directive in conjunction with the optimized `callj` instruction to enable faster calls of leaf procedures. If a procedure is known to call no other procedures, you may define an entry point that skips procedure prolog code (and that does not depend on system-supplied saved context), and declare it as the bal-lab using ``.leafproc'`. If the procedure also has an entry point that goes through the normal prolog, you can specify that entry point as call-lab.

  A ``.leafproc'` declaration is meant for use in conjunction with the optimized call instruction ``callj'`; the directive records the data needed later to choose between converting the ``callj'` into a `bal` or a `call`.

  call-lab is optional; if only one argument is present, or if the two arguments are identical, the single argument is assumed to be the `bal` entry point.

`.sysproc name, index`
  The ``.sysproc'` directive defines a name for a system procedure. After you define it using ``.sysproc'`, you can use name to refer to the system procedure identified by index when calling procedures with the optimized call instruction ``callj'`.

  Both arguments are required; index must be between 0 and 31 (inclusive).

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.16.4 i960 Opcodes

All Intel 960 machine instructions are supported; see section i960 Command-line Options for a discussion of selecting the instruction subset for a particular 960 architecture.

Some opcodes are processed beyond simply emitting a single corresponding instruction: ``callj'`, and Compare-and-Branch or Compare-and-Jump instructions with target displacements larger than 13 bits.

> 9.16.4.1 `callj` |  |
> 9.16.4.2 Compare-and-Branch |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.16.4.1 `callj`

You can write `callj` to have the assembler or the linker determine the most appropriate form of subroutine call: ``call'`, ``bal'`, or ``calls'`. If the assembly source contains enough information--a ``.leafproc'` or ``.sysproc'` directive defining the operand--then `as` translates the `callj`; if not, it simply emits the `callj`, leaving it for the linker to resolve.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.16.4.2 Compare-and-Branch

The 960 architectures provide combined Compare-and-Branch instructions that permit you to store the branch target in the lower 13 bits of the instruction word itself. However, if you specify a branch target far enough away that its address won't fit in 13 bits, the assembler can either issue an error, or convert your Compare-and-Branch instruction into separate instructions to do the compare and the branch.

Whether `as` gives an error or expands the instruction depends on two choices you can make: whether you use the ``-no-relax'` option, and whether you use a "Compare and Branch" instruction or a "Compare and Jump" instruction. The "Jump" instructions are always expanded if necessary; the "Branch" instructions are expanded when necessary unless you specify `-no-relax`---in which case `as` gives an error instead.

These are the Compare-and-Branch instructions, their "Jump" variants, and the instruction pairs they may expand into:

            Compare and
         Branch      Jump       Expanded to
         ------    ------       ------------
            bbc                 chkbit; bno
            bbs                 chkbit; bo
         cmpibe    cmpije       cmpi; be
         cmpibg    cmpijg       cmpi; bg
        cmpibge   cmpijge       cmpi; bge
         cmpibl    cmpijl       cmpi; bl
        cmpible   cmpijle       cmpi; ble
        cmpibno   cmpijno       cmpi; bno
        cmpibne   cmpijne       cmpi; bne
         cmpibo    cmpijo       cmpi; bo
         cmpobe    cmpoje       cmpo; be
         cmpobg    cmpojg       cmpo; bg
        cmpobge   cmpojge       cmpo; bge
         cmpobl    cmpojl       cmpo; bl
        cmpoble   cmpojle       cmpo; ble
        cmpobne   cmpojne       cmpo; bne

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### 9.16.5 Syntax for the i960

> 9.16.5.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.16.5.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.17 IA-64 Dependent Features

> 9.17.1 Options |  |
> 9.17.2 Syntax |  |
> 9.17.3 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.17.1 Options

``-mconstant-gp'`
  This option instructs the assembler to mark the resulting object file as using the "constant GP" model. With this model, it is assumed that the entire program uses a single global pointer (GP) value. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP flag in the ELF file header.

``-mauto-pic'`
  This option instructs the assembler to mark the resulting object file as using the "constant GP without function descriptor" data model. This model is like the "constant GP" model, except that it additionally does away with function descriptors. What this means is that the address of a function refers directly to the function's code entry-point. Normally, such an address would refer to a function descriptor, which contains both the code entry-point and the GP-value needed by the function. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.

``-milp32'`
``-milp64'`
``-mlp64'`
``-mp64'`
  These options select the data model. The assembler defaults to `-mlp64` (LP64 data model).

``-mle'`
``-mbe'`
  These options select the byte order. The `-mle` option selects little-endian byte order (default) and `-mbe` selects big-endian byte order. Note that IA-64 machine code always uses little-endian byte order.

``-mtune=itanium1'`
``-mtune=itanium2'`
  Tune for a particular IA-64 CPU, itanium1 or itanium2. The default is itanium2.

``-munwind-check=warning'`
``-munwind-check=error'`
  These options control what the assembler will do when performing consistency checks on unwind directives. `-munwind-check=warning` will make the assembler issue a warning when an unwind directive check fails. This is the default. `-munwind-check=error` will make the assembler issue an error when an unwind directive check fails.

``-mhint.b=ok'`
``-mhint.b=warning'`
``-mhint.b=error'`
  These options control what the assembler will do when the ``hint.b'` instruction is used. `-mhint.b=ok` will make the assembler accept ``hint.b'`. `-mint.b=warning` will make the assembler issue a warning when ``hint.b'` is used. `-mhint.b=error` will make the assembler treat ``hint.b'` as an error, which is the default.

``-x'`
``-xexplicit'`
  These options turn on dependency violation checking.

``-xauto'`
  This option instructs the assembler to automatically insert stop bits where necessary to remove dependency violations. This is the default mode.

``-xnone'`
  This option turns off dependency violation checking.

``-xdebug'`
  This turns on debug output intended to help tracking down bugs in the dependency violation checker.

``-xdebugn'`
  This is a shortcut for -xnone -xdebug.

``-xdebugx'`
  This is a shortcut for -xexplicit -xdebug.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.17.2 Syntax

The assembler syntax closely follows the IA-64 Assembly Language Reference Guide.

> 9.17.2.1 Special Characters |  |
> 9.17.2.2 Register Names |  |
> 9.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names |  | Bit Names
> 9.17.2.4 Relocations |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.17.2.1 Special Characters

``//'` is the line comment token.

``;'` can be used instead of a newline to separate statements.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.17.2.2 Register Names

The 128 integer registers are referred to as ``rn'`. The 128 floating-point registers are referred to as ``fn'`. The 128 application registers are referred to as ``arn'`. The 128 control registers are referred to as ``crn'`. The 64 one-bit predicate registers are referred to as ``pn'`. The 8 branch registers are referred to as ``bn'`. In addition, the assembler defines a number of aliases: ``gp'` (``r1'`), ``sp'` (``r12'`), ``rp'` (``b0'`), ``ret0'` (``r8'`), ``ret1'` (``r9'`), ``ret2'` (``r10'`), ``ret3'` (``r9'`), ``fargn'` (``f8+n'`), and ``fretn'` (``f8+n'`).

For convenience, the assembler also defines aliases for all named application and control registers. For example, ``ar.bsp'` refers to the register backing store pointer (``ar17'`). Similarly, ``cr.eoi'` refers to the end-of-interrupt register (``cr67'`).

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#### 9.17.2.3 IA-64 Processor-Status-Register (PSR) Bit Names

The assembler defines bit masks for each of the bits in the IA-64 processor status register. For example, ``psr.ic'` corresponds to a value of 0x2000. These masks are primarily intended for use with the ``ssm'`/``sum'` and ``rsm'`/``rum'` instructions, but they can be used anywhere else where an integer constant is expected.

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#### 9.17.2.4 Relocations

In addition to the standard IA-64 relocations, the following relocations are implemented by `as`:

`@slotcount(V)`
  Convert the address offset V into a slot count. This pseudo function is available only on VMS. The expression V must be known at assembly time: it can't reference undefined symbols or symbols in different sections.

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### 9.17.3 Opcodes

For detailed information on the IA-64 machine instruction set, see the IA-64 Architecture Handbook.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

## 9.18 IP2K Dependent Features

> 9.18.1 IP2K Options |  |
> 9.18.2 IP2K Syntax |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.18.1 IP2K Options

The Ubicom IP2K version of `as` has a few machine dependent options:

`-mip2022ext`
  `as` can assemble the extended IP2022 instructions, but it will only do so if this is specifically allowed via this command line option.

`-mip2022`
  This option restores the assembler's default behaviour of not permitting the extended IP2022 instructions to be assembled.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.18.2 IP2K Syntax

> 9.18.2.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.18.2.1 Special Characters

The presence of a ``;'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The IP2K assembler does not currently support a line separator character.

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## 9.19 LM32 Dependent Features

> 9.19.1 Options |  |
> 9.19.2 Syntax |  |
> 9.19.3 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.19.1 Options

`-mmultiply-enabled`
  Enable multiply instructions.

`-mdivide-enabled`
  Enable divide instructions.

`-mbarrel-shift-enabled`
  Enable barrel-shift instructions.

`-msign-extend-enabled`
  Enable sign extend instructions.

`-muser-enabled`
  Enable user defined instructions.

`-micache-enabled`
  Enable instruction cache related CSRs.

`-mdcache-enabled`
  Enable data cache related CSRs.

`-mbreak-enabled`
  Enable break instructions.

`-mall-enabled`
  Enable all instructions and CSRs.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.19.2 Syntax

> 9.19.2.1 Register Names |  |
> 9.19.2.2 Relocatable Expression Modifiers |  |
> 9.19.2.3 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.19.2.1 Register Names

LM32 has 32 x 32-bit general purpose registers ``r0'`, ``r1'`, ... ``r31'`.

The following aliases are defined: ``gp'` - ``r26'`, ``fp'` - ``r27'`, ``sp'` - ``r28'`, ``ra'` - ``r29'`, ``ea'` - ``r30'`, ``ba'` - ``r31'`.

LM32 has the following Control and Status Registers (CSRs).

`IE`
  Interrupt enable.
`IM`
  Interrupt mask.
`IP`
  Interrupt pending.
`ICC`
  Instruction cache control.
`DCC`
  Data cache control.
`CC`
  Cycle counter.
`CFG`
  Configuration.
`EBA`
  Exception base address.
`DC`
  Debug control.
`DEBA`
  Debug exception base address.
`JTX`
  JTAG transmit.
`JRX`
  JTAG receive.
`BP0`
  Breakpoint 0.
`BP1`
  Breakpoint 1.
`BP2`
  Breakpoint 2.
`BP3`
  Breakpoint 3.
`WP0`
  Watchpoint 0.
`WP1`
  Watchpoint 1.
`WP2`
  Watchpoint 2.
`WP3`
  Watchpoint 3.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.19.2.2 Relocatable Expression Modifiers

The assembler supports several modifiers when using relocatable addresses in LM32 instruction operands. The general syntax is the following:

    modifier(relocatable-expression)

`lo`

  This modifier allows you to use bits 0 through 15 of an address expression as 16 bit relocatable expression.

`hi`

  This modifier allows you to use bits 16 through 23 of an address expression as 16 bit relocatable expression.

  For example

      ori  r4, r4, lo(sym+10)
      orhi r4, r4, hi(sym+10)

`gp`

  This modified creates a 16-bit relocatable expression that is the offset of the symbol from the global pointer.

      mva r4, gp(sym)

`got`

  This modifier places a symbol in the GOT and creates a 16-bit relocatable expression that is the offset into the GOT of this symbol.

      lw r4, (gp+got(sym))

`gotofflo16`

  This modifier allows you to use the bits 0 through 15 of an address which is an offset from the GOT.

`gotoffhi16`

  This modifier allows you to use the bits 16 through 31 of an address which is an offset from the GOT.

      orhi r4, r4, gotoffhi16(lsym)
      addi r4, r4, gotofflo16(lsym)

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.19.2.3 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line. Note that if a line starts with a ``#'` character then it can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

A semicolon (``;'`) can be used to separate multiple statements on the same line.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.19.3 Opcodes

For detailed information on the LM32 machine instruction set, see http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/.

`as` implements all the standard LM32 opcodes.

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## 9.20 M32C Dependent Features

`as` can assemble code for several different members of the Renesas M32C family. Normally the default is to assemble code for the M16C microprocessor. The `-m32c` option may be used to change the default to the M32C microprocessor.

> 9.20.1 M32C Options |  |
> 9.20.2 M32C Syntax |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.20.1 M32C Options

The Renesas M32C version of `as` has these machine-dependent options:

`-m32c`
  Assemble M32C instructions.

`-m16c`
  Assemble M16C instructions (default).

`-relax`
  Enable support for link-time relaxations.

`-h-tick-hex`
  Support H'00 style hex constants in addition to 0x00 style.

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### 9.20.2 M32C Syntax

> 9.20.2.1 Symbolic Operand Modifiers |  |
> 9.20.2.2 Special Characters |  |

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#### 9.20.2.1 Symbolic Operand Modifiers

The assembler supports several modifiers when using symbol addresses in M32C instruction operands. The general syntax is the following:

    %modifier(symbol)

`%dsp8`
`%dsp16`

  These modifiers override the assembler's assumptions about how big a symbol's address is. Normally, when it sees an operand like ``sym[a0]'` it assumes ``sym'` may require the widest displacement field (16 bits for ``-m16c'`, 24 bits for ``-m32c'`). These modifiers tell it to assume the address will fit in an 8 or 16 bit (respectively) unsigned displacement. Note that, of course, if it doesn't actually fit you will get linker errors. Example:

      mov.w %dsp8(sym)[a0],r1
      mov.b #0,%dsp8(sym)[a0]

`%hi8`

  This modifier allows you to load bits 16 through 23 of a 24 bit address into an 8 bit register. This is useful with, for example, the M16C ``smovf'` instruction, which expects a 20 bit address in ``r1h'` and ``a0'`. Example:

      mov.b #%hi8(sym),r1h
      mov.w #%lo16(sym),a0
      smovf.b

`%lo16`

  Likewise, this modifier allows you to load bits 0 through 15 of a 24 bit address into a 16 bit register.

`%hi16`

  This modifier allows you to load bits 16 through 31 of a 32 bit address into a 16 bit register. While the M32C family only has 24 bits of address space, it does support addresses in pairs of 16 bit registers (like ``a1a0'` for the ``lde'` instruction). This modifier is for loading the upper half in such cases. Example:

      mov.w #%hi16(sym),a1
      mov.w #%lo16(sym),a0
      ...
      lde.w [a1a0],r1

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#### 9.20.2.2 Special Characters

The presence of a ``;'` character on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``|'` character can be used to separate statements on the same line.

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## 9.21 M32R Dependent Features

> 9.21.1 M32R Options |  |
> 9.21.2 M32R Directives |  |
> 9.21.3 M32R Warnings |  |

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### 9.21.1 M32R Options

The Renease M32R version of `as` has a few machine dependent options:

`-m32rx`
  `as` can assemble code for several different members of the Renesas M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions.

`-m32r2`
  This option changes the target processor to the M32R2 microprocessor.

`-m32r`
  This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option.

`-little`
  This option tells the assembler to produce little-endian code and data. The default is dependent upon how the toolchain was configured.

`-EL`
  This is a synonym for -little.

`-big`
  This option tells the assembler to produce big-endian code and data.

`-EB`
  This is a synonum for -big.

`-KPIC`
  This option specifies that the output of the assembler should be marked as position-independent code (PIC).

`-parallel`
  This option tells the assembler to attempts to combine two sequential instructions into a single, parallel instruction, where it is legal to do so.

`-no-parallel`
  This option disables a previously enabled -parallel option.

`-no-bitinst`
  This option disables the support for the extended bit-field instructions provided by the M32R2. If this support needs to be re-enabled the -bitinst switch can be used to restore it.

`-O`
  This option tells the assembler to attempt to optimize the instructions that it produces. This includes filling delay slots and converting sequential instructions into parallel ones. This option implies -parallel.

`-warn-explicit-parallel-conflicts`
  Instructs `as` to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but `gcc` disables it when it invokes `as` directly. Questionable instructions are those whose behaviour would be different if they were executed sequentially. For example the code fragment ``mv r1, r2 || mv r3, r1'` produces a different result from ``mv r1, r2 \n mv r3, r1'` since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3.

`-Wp`
  This is a shorter synonym for the -warn-explicit-parallel-conflicts option.

`-no-warn-explicit-parallel-conflicts`
  Instructs `as` not to produce warning messages when questionable parallel instructions are encountered.

`-Wnp`
  This is a shorter synonym for the -no-warn-explicit-parallel-conflicts option.

`-ignore-parallel-conflicts`
  This option tells the assembler's to stop checking parallel instructions for constraint violations. This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances.

`-no-ignore-parallel-conflicts`
  This option restores the assembler's default behaviour of checking parallel instructions to detect constraint violations.

`-Ip`
  This is a shorter synonym for the -ignore-parallel-conflicts option.

`-nIp`
  This is a shorter synonym for the -no-ignore-parallel-conflicts option.

`-warn-unmatched-high`
  This option tells the assembler to produce a warning message if a `.high` pseudo op is encountered without a matching `.low` pseudo op. The presence of such an unmatched pseudo op usually indicates a programming error.

`-no-warn-unmatched-high`
  Disables a previously enabled -warn-unmatched-high option.

`-Wuh`
  This is a shorter synonym for the -warn-unmatched-high option.

`-Wnuh`
  This is a shorter synonym for the -no-warn-unmatched-high option.

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### 9.21.2 M32R Directives

The Renease M32R version of `as` has a few architecture specific directives:

`low expression`
  The `low` directive computes the value of its expression and places the lower 16-bits of the result into the immediate-field of the instruction. For example:

         or3   r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
         add3, r0, r0, #low(fred)   ; compute r0 = r0 + low 16-bits of address of fred

`high expression`
  The `high` directive computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. For example:

         seth  r0, #high(0x12345678) ; compute r0 = 0x12340000
         seth, r0, #high(fred)       ; compute r0 = upper 16-bits of address of fred

`shigh expression`
  The `shigh` directive is very similar to the `high` directive. It also computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. The difference is that `shigh` also checks to see if the lower 16-bits could be interpreted as a signed number, and if so it assumes that a borrow will occur from the upper-16 bits. To compensate for this the `shigh` directive pre-biases the upper 16 bit value by adding one to it. For example:

  For example:

         seth  r0, #shigh(0x12345678) ; compute r0 = 0x12340000
         seth  r0, #shigh(0x00008000) ; compute r0 = 0x00010000

  In the second example the lower 16-bits are 0x8000. If these are treated as a signed value and sign extended to 32-bits then the value becomes 0xffff8000. If this value is then added to 0x00010000 then the result is 0x00008000.

  This behaviour is to allow for the different semantics of the `or3` and `add3` instructions. The `or3` instruction treats its 16-bit immediate argument as unsigned whereas the `add3` treats its 16-bit immediate as a signed value. So for example:

         seth  r0, #shigh(0x00008000)
         add3  r0, r0, #low(0x00008000)

  Produces the correct result in r0, whereas:

         seth  r0, #shigh(0x00008000)
         or3   r0, r0, #low(0x00008000)

  Stores 0xffff8000 into r0.

  Note - the `shigh` directive does not know where in the assembly source code the lower 16-bits of the value are going set, so it cannot check to make sure that an `or3` instruction is being used rather than an `add3` instruction. It is up to the programmer to make sure that correct directives are used.

`.m32r`
  The directive performs a similar thing as the -m32r command line option. It tells the assembler to only accept M32R instructions from now on. An instructions from later M32R architectures are refused.

`.m32rx`
  The directive performs a similar thing as the -m32rx command line option. It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA.

`.m32r2`
  The directive performs a similar thing as the -m32r2 command line option. It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA.

`.little`
  The directive performs a similar thing as the -little command line option. It tells the assembler to start producing little-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger.

`.big`
  The directive performs a similar thing as the -big command line option. It tells the assembler to start producing big-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger.

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### 9.21.3 M32R Warnings

There are several warning and error messages that can be produced by `as` which are specific to the M32R:

`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?`
  This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment ``mv r1, r2 || neg r3, r1'` register r1 is the destination of the move instruction and the input to the neg instruction.

`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?`
  This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment ``mv r1, r2 || neg r2, r3'` register r2 is the destination of the neg instruction and the input to the move instruction.

`instruction ``...'` is for the M32RX only`
  This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the ``-m32rx'` command line flag has not been specified to allow assembly of such instructions.

`unknown instruction ``...'``
  This message is produced when the assembler encounters an instruction which it does not recognize.

`only the NOP instruction can be issued in parallel on the m32r`
  This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the ``-m32rx'` command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel.

`instruction ``...'` cannot be executed in parallel.`
  This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel.

`Instructions share the same execution pipeline`
  This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline.

`Instructions write to the same destination register.`
  This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: ``mv r1, r2 || neg r1, r3'` ``jl r0 || mv r14, r1'` ``st r2, @-r1 || mv r1, r3'` ``mv r1, r2 || ld r0, @r1+'` ``cmp r1, r2 || addx r3, r4'` (Both write to the condition bit)

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## 9.22 M680x0 Dependent Features

> 9.22.1 M680x0 Options |  |
> 9.22.2 Syntax |  |
> 9.22.3 Motorola Syntax |  |
> 9.22.4 Floating Point |  |
> 9.22.5 680x0 Machine Directives |  |
> 9.22.6 Opcodes |  |

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### 9.22.1 M680x0 Options

The Motorola 680x0 version of `as` has a few machine dependent options:

``-march=architecture'`
  This option specifies a target architecture. The following architectures are recognized: `68000`, `68010`, `68020`, `68030`, `68040`, `68060`, `cpu32`, `isaa`, `isaaplus`, `isab`, `isac` and `cfv4e`.

``-mcpu=cpu'`
  This option specifies a target cpu. When used in conjunction with the ``-march'` option, the cpu must be within the specified architecture. Also, the generic features of the architecture are used for instruction generation, rather than those of the specific chip.

``-m[no-]68851'`
``-m[no-]68881'`
``-m[no-]div'`
``-m[no-]usp'`
``-m[no-]float'`
``-m[no-]mac'`
``-m[no-]emac'`

  Enable or disable various architecture specific features. If a chip or architecture by default supports an option (for instance ``-march=isaaplus'` includes the ``-mdiv'` option), explicitly disabling the option will override the default.

``-l'`
  You can use the ``-l'` option to shorten the size of references to undefined symbols. If you do not use the ``-l'` option, references to undefined symbols are wide enough for a full `long` (32 bits). (Since `as` cannot know where these symbols end up, `as` can only allocate space for the linker to fill in later. Since `as` does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away.

``--register-prefix-optional'`
  For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a ``%'` before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named ``a0'` through ``a7'`, and so on. The ``%'` is always accepted, but is not required for certain configurations, notably ``sun3'`. The ``--register-prefix-optional'` option may be used to permit omitting the ``%'` even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names.

``--bitwise-or'`
  Normally the character ``|'` is treated as a comment character, which means that it can not be used in expressions. The ``--bitwise-or'` option turns ``|'` into a normal character. In this mode, you must either use C style comments, or start comments with a ``#'` character at the beginning of a line.

``--base-size-default-16 --base-size-default-32'`
  If you use an addressing mode with a base register without specifying the size, `as` will normally use the full 32 bit value. For example, the addressing mode ``%a0@(%d0)'` is equivalent to ``%a0@(%d0:l)'`. You may use the ``--base-size-default-16'` option to tell `as` to default to using the 16 bit value. In this case, ``%a0@(%d0)'` is equivalent to ``%a0@(%d0:w)'`. You may use the ``--base-size-default-32'` option to restore the default behaviour.

``--disp-size-default-16 --disp-size-default-32'`
  If you use an addressing mode with a displacement, and the value of the displacement is not known, `as` will normally assume that the value is 32 bits. For example, if the symbol ``disp'` has not been defined, `as` will assemble the addressing mode ``%a0@(disp,%d0)'` as though ``disp'` is a 32 bit value. You may use the ``--disp-size-default-16'` option to tell `as` to instead assume that the displacement is 16 bits. In this case, `as` will assemble ``%a0@(disp,%d0)'` as though ``disp'` is a 16 bit value. You may use the ``--disp-size-default-32'` option to restore the default behaviour.

``--pcrel'`
  Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors they are limited to word displacements maximum. When `as` needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word branches will be emitted. An error message will be generated if a word branch cannot reach its target. This option has no effect on 68020 and other processors that have long branches. see section Branch Improvement.

``-m68000'`
  `as` can assemble code for several different members of the Motorola 680x0 family. The default depends upon how `as` was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals.

  ``-m68000'`
  ``-m68ec000'`
  ``-m68hc000'`
  ``-m68hc001'`
  ``-m68008'`
  ``-m68302'`
  ``-m68306'`
  ``-m68307'`
  ``-m68322'`
  ``-m68356'`
    Assemble for the 68000. ``-m68008'`, ``-m68302'`, and so on are synonyms for ``-m68000'`, since the chips are the same from the point of view of the assembler.

  ``-m68010'`
    Assemble for the 68010.

  ``-m68020'`
  ``-m68ec020'`
    Assemble for the 68020. This is normally the default.

  ``-m68030'`
  ``-m68ec030'`
    Assemble for the 68030.

  ``-m68040'`
  ``-m68ec040'`
    Assemble for the 68040.

  ``-m68060'`
  ``-m68ec060'`
    Assemble for the 68060.

  ``-mcpu32'`
  ``-m68330'`
  ``-m68331'`
  ``-m68332'`
  ``-m68333'`
  ``-m68334'`
  ``-m68336'`
  ``-m68340'`
  ``-m68341'`
  ``-m68349'`
  ``-m68360'`
    Assemble for the CPU32 family of chips.

  ``-m5200'`
  ``-m5202'`
  ``-m5204'`
  ``-m5206'`
  ``-m5206e'`
  ``-m521x'`
  ``-m5249'`
  ``-m528x'`
  ``-m5307'`
  ``-m5407'`
  ``-m547x'`
  ``-m548x'`
  ``-mcfv4'`
  ``-mcfv4e'`
    Assemble for the ColdFire family of chips.

  ``-m68881'`
  ``-m68882'`
    Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions.

  ``-mno-68881'`
    Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used.

  ``-m68851'`
    Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; ``-m68851'` and ``-m68040'` should not be used together.

  ``-mno-68851'`
    Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.

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### 9.22.2 Syntax

This syntax for the Motorola 680x0 was developed at MIT.

The 680x0 version of `as` uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, ``movl'` is equivalent to ``mov.l'`.

In the following table apc stands for any of the address registers (``%a0'` through ``%a7'`), the program counter (``%pc'`), the zero-address relative to the program counter (``%zpc'`), a suppressed address register (``%za0'` through ``%za7'`), or it may be omitted entirely. The use of size means one of ``w'` or ``l'`, and it may be omitted, along with the leading colon, unless a scale is also specified. The use of scale means one of ``1'`, ``2'`, ``4'`, or ``8'`, and it may always be omitted along with the leading colon.

The following addressing modes are understood:

Immediate
  ``#number'`

Data Register
  ``%d0'` through ``%d7'`

Address Register
  ``%a0'` through ``%a7'`
  ``%a7'` is also known as ``%sp'`, i.e., the Stack Pointer. `%a6` is also known as ``%fp'`, the Frame Pointer.

Address Register Indirect
  ``%a0@'` through ``%a7@'`

Address Register Postincrement
  ``%a0@+'` through ``%a7@+'`

Address Register Predecrement
  ``%a0@-'` through ``%a7@-'`

Indirect Plus Offset
  ``apc@(number)'`

Index
  ``apc@(number,register:size:scale)'`

  The number may be omitted.

Postindex
  ``apc@(number)@(onumber,register:size:scale)'`

  The onumber or the register, but not both, may be omitted.

Preindex
  ``apc@(number,register:size:scale)@(onumber)'`

  The number may be omitted. Omitting the register produces the Postindex addressing mode.

Absolute
  ``symbol'`, or ``digits'`, optionally followed by ``:b'`, ``:w'`, or ``:l'`.

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### 9.22.3 Motorola Syntax

The standard Motorola syntax for this chip differs from the syntax already discussed (see section Syntax). `as` can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible.

In the following table apc stands for any of the address registers (``%a0'` through ``%a7'`), the program counter (``%pc'`), the zero-address relative to the program counter (``%zpc'`), or a suppressed address register (``%za0'` through ``%za7'`). The use of size means one of ``w'` or ``l'`, and it may always be omitted along with the leading dot. The use of scale means one of ``1'`, ``2'`, ``4'`, or ``8'`, and it may always be omitted along with the leading asterisk.

The following additional addressing modes are understood:

Address Register Indirect
  ``(%a0)'` through ``(%a7)'`
  ``%a7'` is also known as ``%sp'`, i.e., the Stack Pointer. `%a6` is also known as ``%fp'`, the Frame Pointer.

Address Register Postincrement
  ``(%a0)+'` through ``(%a7)+'`

Address Register Predecrement
  ``-(%a0)'` through ``-(%a7)'`

Indirect Plus Offset
  ``number(%a0)'` through ``number(%a7)'`, or ``number(%pc)'`.

  The number may also appear within the parentheses, as in ``(number,%a0)'`. When used with the pc, the number may be omitted (with an address register, omitting the number produces Address Register Indirect mode).

Index
  ``number(apc,register.size*scale)'`

  The number may be omitted, or it may appear within the parentheses. The apc may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

Postindex
  ``([number,apc],register.size*scale,onumber)'`

  The onumber, or the register, or both, may be omitted. Either the number or the apc may be omitted, but not both.

Preindex
  ``([number,apc,register.size*scale],onumber)'`

  The number, or the apc, or the register, or any two of them, may be omitted. The onumber may be omitted. The register and the apc may appear in either order. If both apc and register are address registers, and the size and scale are omitted, then the first register is taken as the base register, and the second as the index register.

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### 9.22.4 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

`.float`
  `Single` precision floating point constants.

`.double`
  `Double` precision floating point constants.

`.extend`
`.ldouble`
  `Extended` precision (`long double`) floating point constants.

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### 9.22.5 680x0 Machine Directives

In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives.

`.data1`
  This directive is identical to a `.data 1` directive.

`.data2`
  This directive is identical to a `.data 2` directive.

`.even`
  This directive is a special case of the `.align` directive; it aligns the output to an even byte boundary.

`.skip`
  This directive is identical to a `.space` directive.

`.arch name`
  Select the target architecture and extension features. Valid values for name are the same as for the ``-march'` command line option. This directive cannot be specified after any instructions have been assembled. If it is given multiple times, or in conjunction with the ``-march'` option, all uses must be for the same architecture and extension set.

`.cpu name`
  Select the target cpu. Valid valuse for name are the same as for the ``-mcpu'` command line option. This directive cannot be specified after any instructions have been assembled. If it is given multiple times, or in conjunction with the ``-mopt'` option, all uses must be for the same cpu.

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### 9.22.6 Opcodes

> 9.22.6.1 Branch Improvement |  |
> 9.22.6.2 Special Characters |  |

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#### 9.22.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting ``j'` for ``b'` at the start of a Motorola mnemonic.

The following table summarizes the pseudo-operations. A `*` flags cases that are more fully described after the table:

              Displacement
              +------------------------------------------------------------
              |                68020           68000/10, not PC-relative OK
    Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
              +------------------------------------------------------------
         jbsr |bsrs    bsrw    bsrl            jsr
          jra |bras    braw    bral            jmp
    *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
    *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
         fjXX | N/A    fbXXw   fbXXl            N/A

    XX: condition
    NX: negative of condition XX

`*`---see full description below
`**`---this expansion mode is disallowed by ``--pcrel'`

`jbsr`
`jra`
  These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the ``--pcrel'` option is not given, an absolute long jump will be emitted instead. If no long branches are available, the ``--pcrel'` option is given, and a word branch cannot reach the target, an error message is generated.

  In addition to standard branch operands, `as` allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction.

`jXX`
  Here, ``jXX'` stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

       jhi   jls   jcc   jcs   jne   jeq   jvc
       jvs   jpl   jmi   jge   jlt   jgt   jle

  Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long branches are available, and the ``--pcrel'` option is not given, `as` issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions:

          jXX foo

  gives

           bNXs oof
           jmp foo
       oof:

`dbXX`
  The full family of pseudo-operations covered here is

       dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
       dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
       dbf    dbra   dbt

  Motorola ``dbXX'` instructions allow word displacements only. When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, when the source reads ``dbXX foo'`, `as` emits

           dbXX oo1
           bras oo2
       oo1:bral foo
       oo2:

  If, however, long branches are not available and the ``--pcrel'` option is not given, `as` emits

           dbXX oo1
           bras oo2
       oo1:jmp foo
       oo2:

`fjXX`
  This family includes

       fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
       fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
       fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
       fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
       fjugt  fjule  fjult  fjun

  Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.

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#### 9.22.6.2 Special Characters

Line comments are introduced by the ``|'` character appearing anywhere on a line, unless the ``--bitwise-or'` command line option has been specified.

An asterisk (``*'`) as the first character on a line marks the start of a line comment as well.

A hash character (``#'`) as the first character on a line also marks the start of a line comment, but in this case it could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing). If the hash character appears elsewhere on a line it is used to introduce an immediate value. (This is for compatibility with Sun's assembler).

Multiple statements on the same line can appear if they are separated by the ``;'` character.

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## 9.23 M68HC11 and M68HC12 Dependent Features

> 9.23.1 M68HC11 and M68HC12 Options |  |
> 9.23.2 Syntax |  |
> 9.23.3 Symbolic Operand Modifiers |  |
> 9.23.4 Assembler Directives |  |
> 9.23.5 Floating Point |  |
> 9.23.6 Opcodes |  |

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### 9.23.1 M68HC11 and M68HC12 Options

The Motorola 68HC11 and 68HC12 version of `as` have a few machine dependent options.

`-m68hc11`
  This option switches the assembler into the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11.

`-m68hc12`
  This option switches the assembler into the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications.

`-m68hcs12`
  This option switches the assembler into the M68HCS12 mode. This mode is similar to ``-m68hc12'` but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the ``movb'` and ``movw'` instruction when a PC-relative operand is used.

`-mm9s12x`
  This option switches the assembler into the M9S12X mode. This mode is similar to ``-m68hc12'` but specifies to assemble for the S12X series which is a superset of the HCS12.

`-mm9s12xg`
  This option switches the assembler into the XGATE mode for the RISC co-processor featured on some S12X-family chips.

`--xgate-ramoffset`
  This option instructs the linker to offset RAM addresses from S12X address space into XGATE address space.

`-mshort`
  This option controls the ABI and indicates to use a 16-bit integer ABI. It has no effect on the assembled instructions. This is the default.

`-mlong`
  This option controls the ABI and indicates to use a 32-bit integer ABI.

`-mshort-double`
  This option controls the ABI and indicates to use a 32-bit float ABI. This is the default.

`-mlong-double`
  This option controls the ABI and indicates to use a 64-bit float ABI.

`--strict-direct-mode`
  You can use the ``--strict-direct-mode'` option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the ``clr'` instruction does not support direct page mode addressing. When it is used with the direct page mode, `as` will ignore it and generate an absolute addressing. This option prevents `as` from doing this, and the wrong usage of the direct page mode will raise an error.

`--short-branches`
  The ``--short-branches'` option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default `as` transforms the relative branch (``bsr'`, ``bgt'`, ``bge'`, ``beq'`, ``bne'`, ``ble'`, ``blt'`, ``bhi'`, ``bcc'`, ``bls'`, ``bcs'`, ``bmi'`, ``bvs'`, ``bvs'`, ``bra'`) into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the ``bsr'` instruction is translated into a ``jsr'`, the ``bra'` instruction is translated into a ``jmp'` and the conditional branches instructions are inverted and followed by a ``jmp'`. This option disables these translations and `as` will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the ``jbra'`, ``jbsr'` and ``jbXX'` pseudo opcodes.

`--force-long-branches`
  The ``--force-long-branches'` option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the ``jbra'`, ``jbsr'` and ``jbXX'` pseudo opcodes.

`--print-insn-syntax`
  You can use the ``--print-insn-syntax'` option to obtain the syntax description of the instruction when an error is detected.

`--print-opcodes`
  The ``--print-opcodes'` option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed `as` exits.

`--generate-example`
  The ``--generate-example'` option is similar to ``--print-opcodes'` but it generates an example for each instruction instead.

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### 9.23.2 Syntax

In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (``,'`). In the normal mode, `as` will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with ``-M'` option), it will treat them as comments. Example:

    inx
    lda  #23
    bset 2,x #4
    brclr *bot #8 foo

The presence of a ``;'` character or a ``!'` character anywhere on a line indicates the start of a comment that extends to the end of that line.

A ``*'` or a ``#'` character at the start of a line also introduces a line comment, but these characters do not work elsewhere on the line. If the first character of the line is a ``#'` then as well as starting a comment, the line could also be logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The M68HC11 assembler does not currently support a line separator character.

The following addressing modes are understood for 68HC11 and 68HC12:

Immediate
  ``#number'`

Address Register
  ``number,X'`, ``number,Y'`

  The number may be omitted in which case 0 is assumed.

Direct Addressing mode
  ``*symbol'`, or ``*digits'`

Absolute
  ``symbol'`, or ``digits'`

The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below:

Constant Offset Indexed Addressing Mode
  ``number,reg'`

  The number may be omitted in which case 0 is assumed. The register can be either ``X'`, ``Y'`, ``SP'` or ``PC'`. The assembler will use the smaller post-byte definition according to the constant value (5-bit constant offset, 9-bit constant offset or 16-bit constant offset). If the constant is not known by the assembler it will use the 16-bit constant offset post-byte and the value will be resolved at link time.

Offset Indexed Indirect
  ``[number,reg]'`

  The register can be either ``X'`, ``Y'`, ``SP'` or ``PC'`.

Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement
  ``number,-reg'` ``number,+reg'` ``number,reg-'` ``number,reg+'`

  The number must be in the range ``-8'`..``+8'` and must not be 0. The register can be either ``X'`, ``Y'`, ``SP'` or ``PC'`.

Accumulator Offset
  ``acc,reg'`

  The accumulator register can be either ``A'`, ``B'` or ``D'`. The register can be either ``X'`, ``Y'`, ``SP'` or ``PC'`.

Accumulator D offset indexed-indirect
  ``[D,reg]'`

  The register can be either ``X'`, ``Y'`, ``SP'` or ``PC'`.

For example:

    ldab 1024,sp
    ldd [10,x]
    orab 3,+x
    stab -2,y-
    ldx a,pc
    sty [d,sp]

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### 9.23.3 Symbolic Operand Modifiers

The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following:

    %modifier(symbol)

`%addr`
  This modifier indicates to the assembler and linker to use the 16-bit physical address corresponding to the symbol. This is intended to be used on memory window systems to map a symbol in the memory bank window. If the symbol is in a memory expansion part, the physical address corresponds to the symbol address within the memory bank window. If the symbol is not in a memory expansion part, this is the symbol address (using or not using the %addr modifier has no effect in that case).

`%page`
  This modifier indicates to use the memory page number corresponding to the symbol. If the symbol is in a memory expansion part, its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window. If the symbol is not in a memory expansion part, the page number is 0.

`%hi`
  This modifier indicates to use the 8-bit high part of the physical address of the symbol.

`%lo`
  This modifier indicates to use the 8-bit low part of the physical address of the symbol.

For example a 68HC12 call to a function ``foo_example'` stored in memory expansion part could be written as follows:

    call %addr(foo_example),%page(foo_example)

and this is equivalent to

    call foo_example

And for 68HC11 it could be written as follows:

    ldab #%page(foo_example)
    stab _page_switch
    jsr  %addr(foo_example)

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### 9.23.4 Assembler Directives

The 68HC11 and 68HC12 version of `as` have the following specific assembler directives:

`.relax`
  The relax directive is used by the ``GNU Compiler'` to emit a specific relocation to mark a group of instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed.

`.mode [mshort|mlong|mshort-double|mlong-double]`
  This directive specifies the ABI. It overrides the ``-mshort'`, ``-mlong'`, ``-mshort-double'` and ``-mlong-double'` options.

`.far symbol`
  This directive marks the symbol as a ``far'` symbol meaning that it uses a ``call/rtc'` calling convention as opposed to ``jsr/rts'`. During a final link, the linker will identify references to the ``far'` symbol and will verify the proper calling convention.

`.interrupt symbol`
  This directive marks the symbol as an interrupt entry point. This information is then used by the debugger to correctly unwind the frame across interrupts.

`.xrefb symbol`
  This directive is defined for compatibility with the ``Specification for Motorola 8 and 16-Bit Assembly Language Input Standard'` and is ignored.

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### 9.23.5 Floating Point

Packed decimal (P) format floating literals are not supported. Feel free to add the code!

The floating point formats generated by directives are these.

`.float`
  `Single` precision floating point constants.

`.double`
  `Double` precision floating point constants.

`.extend`
`.ldouble`
  `Extended` precision (`long double`) floating point constants.

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### 9.23.6 Opcodes

> 9.23.6.1 Branch Improvement |  |

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#### 9.23.6.1 Branch Improvement

Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending ``j'` to the start of Motorola mnemonic. These pseudo opcodes are not affected by the ``--short-branches'` or ``--force-long-branches'` options.

The following table summarizes the pseudo-operations.

                            Displacement Width
         +-------------------------------------------------------------+
         |                     Options                                 |
         |    --short-branches           --force-long-branches         |
         +--------------------------+----------------------------------+
      Op |BYTE             WORD     | BYTE          WORD               |
         +--------------------------+----------------------------------+
     bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
     bra | bra <pc-rel>    <error>  |               jmp <abs>          |
    jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
    jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
     bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
    jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
         |                jmp <abs> |                                  |
         +--------------------------+----------------------------------+
    XX: condition
    NX: negative of condition XX

`jbsr`
`jbra`
  These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target.

`jbXX`
  Here, ``jbXX'` stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is:

       jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
       jbcs   jbne   jblt   jble   jbls   jbvc   jbmi

  For the cases of non-PC relative displacements and long displacements, `as` issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case:

          jbXX foo

  gives

           bNXs oof
           jmp foo
       oof:

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## 9.24 MicroBlaze Dependent Features

The Xilinx MicroBlaze processor family includes several variants, all using the same core instruction set. This chapter covers features of the GNU assembler that are specific to the MicroBlaze architecture. For details about the MicroBlaze instruction set, please see the MicroBlaze Processor Reference Guide (UG081) available at www.xilinx.com.

> 9.24.1 Directives |  | Directives for MicroBlaze Processors.
> 9.24.2 Syntax for the MicroBlaze |  |

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### 9.24.1 Directives

A number of assembler directives are available for MicroBlaze.

`.data8 expression,...`
  This directive is an alias for `.byte`. Each expression is assembled into an eight-bit value.

`.data16 expression,...`
  This directive is an alias for `.hword`. Each expression is assembled into an 16-bit value.

`.data32 expression,...`
  This directive is an alias for `.word`. Each expression is assembled into an 32-bit value.

`.ent name[,label]`
  This directive is an alias for `.func` denoting the start of function name at (optional) label.

`.end name[,label]`
  This directive is an alias for `.endfunc` denoting the end of function name.

`.gpword label,...`
  This directive is an alias for `.rva`. The resolved address of label is stored in the data section.

`.weakext label`
  Declare that label is a weak external symbol.

`.rodata`
  Switch to .rodata section. Equivalent to `.section .rodata`

`.sdata2`
  Switch to .sdata2 section. Equivalent to `.section .sdata2`

`.sdata`
  Switch to .sdata section. Equivalent to `.section .sdata`

`.bss`
  Switch to .bss section. Equivalent to `.section .bss`

`.sbss`
  Switch to .sbss section. Equivalent to `.section .sbss`

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### 9.24.2 Syntax for the MicroBlaze

> 9.24.2.1 Special Characters |  |

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#### 9.24.2.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.25 MIPS Dependent Features

GNU `as` for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the MIPS instruction set, see MIPS RISC Architecture, by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work.

> 9.25.1 Assembler options |  |
> 9.25.2 High-level assembly macros |  |
> 9.25.3 Directives to override the size of symbols |  |
> 9.25.4 Controlling the use of small data accesses |  |
> 9.25.5 Directives to override the ISA level |  |
> 9.25.6 Directives to control code generation |  |
> 9.25.7 Directives for extending MIPS 16 bit instructions |  |
> 9.25.8 Directive to mark data as an instruction |  |
> 9.25.9 Directives to record which NaN encoding is being used |  |
> 9.25.10 Directives to save and restore options |  |
> 9.25.11 Directives to control generation of MIPS ASE instructions |  |
> 9.25.12 Directives to override floating-point options |  |
> 9.25.13 Syntactical considerations for the MIPS assembler |  | MIPS specific syntactical considerations

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### 9.25.1 Assembler options

The MIPS configurations of GNU `as` support these special options:

`-G num`
  Set the "small data" limit to n bytes. The default limit is 8 bytes. See section Controlling the use of small data accesses.

`-EB`
`-EL`
  Any MIPS configuration of `as` can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use ``-EB'` to select big-endian output, and ``-EL'` for little-endian.

`-KPIC`
  Generate SVR4-style PIC. This option tells the assembler to generate SVR4-style position-independent macro expansions. It also tells the assembler to mark the output file as PIC.

`-mvxworks-pic`
  Generate VxWorks PIC. This option tells the assembler to generate VxWorks-style position-independent macro expansions.

`-mips1`
`-mips2`
`-mips3`
`-mips4`
`-mips5`
`-mips32`
`-mips32r2`
`-mips64`
`-mips64r2`
  Generate code for a particular MIPS Instruction Set Architecture level. ``-mips1'` corresponds to the R2000 and R3000 processors, ``-mips2'` to the R6000 processor, ``-mips3'` to the R4000 processor, and ``-mips4'` to the R8000 and R10000 processors. ``-mips5'`, ``-mips32'`, ``-mips32r2'`, ``-mips64'`, and ``-mips64r2'` correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see Directives to override the ISA level.

`-mgp32`
`-mfp32`
  Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. ``-mgp32'` controls the size of general-purpose registers and ``-mfp32'` controls the size of floating-point registers.

  The `.set gp=32` and `.set fp=32` directives allow the size of registers to be changed for parts of an object. The default value is restored by `.set gp=default` and `.set fp=default`.

  On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers.

`-mgp64`
`-mfp64`
  Assume that 64-bit registers are available. This is provided in the interests of symmetry with ``-mgp32'` and ``-mfp32'`.

  The `.set gp=64` and `.set fp=64` directives allow the size of registers to be changed for parts of an object. The default value is restored by `.set gp=default` and `.set fp=default`.

`-mips16`
`-no-mips16`
  Generate code for the MIPS 16 processor. This is equivalent to putting `.set mips16` at the start of the assembly file. ``-no-mips16'` turns off this option.

`-mmicromips`
`-mno-micromips`
  Generate code for the microMIPS processor. This is equivalent to putting `.set micromips` at the start of the assembly file. ``-mno-micromips'` turns off this option. This is equivalent to putting `.set nomicromips` at the start of the assembly file.

`-msmartmips`
`-mno-smartmips`
  Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications. This is equivalent to putting `.set smartmips` at the start of the assembly file. ``-mno-smartmips'` turns off this option.

`-mips3d`
`-no-mips3d`
  Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. ``-no-mips3d'` turns off this option.

`-mdmx`
`-no-mdmx`
  Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. ``-no-mdmx'` turns off this option.

`-mdsp`
`-mno-dsp`
  Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. ``-mno-dsp'` turns off this option.

`-mdspr2`
`-mno-dspr2`
  Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. ``-mno-dspr2'` turns off this option.

`-mmt`
`-mno-mt`
  Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. ``-mno-mt'` turns off this option.

`-mmcu`
`-mno-mcu`
  Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. ``-mno-mcu'` turns off this option.

`-mmsa`
`-mno-msa`
  Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. ``-mno-msa'` turns off this option.

`-mvirt`
`-mno-virt`
  Generate code for the Virtualization Application Specific Extension. This tells the assembler to accept Virtualization instructions. ``-mno-virt'` turns off this option.

`-minsn32`
`-mno-insn32`
  Only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. This is equivalent to putting `.set insn32` at the start of the assembly file. ``-mno-insn32'` turns off this option. This is equivalent to putting `.set noinsn32` at the start of the assembly file. By default ``-mno-insn32'` is selected, allowing all instructions to be used.

`-mfix7000`
`-mno-fix7000`
  Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.

`-mfix-rm7000`
`-mno-fix-rm7000`
  Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction.

`-mfix-loongson2f-jump`
`-mno-fix-loongson2f-jump`
  Eliminate instruction fetch from outside 256M region to work around the Loongson2F ``jump'` instructions. Without it, under extreme cases, the kernel may crash. The issue has been solved in latest processor batches, but this fix has no side effect to them.

`-mfix-loongson2f-nop`
`-mno-fix-loongson2f-nop`
  Replace nops by `or at,at,zero` to work around the Loongson2F ``nop'` errata. Without it, under extreme cases, the CPU might deadlock. The issue has been solved in later Loongson2F batches, but this fix has no side effect to them.

`-mfix-vr4120`
`-mno-fix-vr4120`
  Insert nops to work around certain VR4120 errata. This option is intended to be used on GCC-generated code: it is not designed to catch all problems in hand-written assembler code.

`-mfix-vr4130`
`-mno-fix-vr4130`
  Insert nops to work around the VR4130 ``mflo'`/``mfhi'` errata.

`-mfix-24k`
`-mno-fix-24k`
  Insert nops to work around the 24K ``eret'`/``deret'` errata.

`-mfix-cn63xxp1`
`-mno-fix-cn63xxp1`
  Replace `pref` hints 0 - 4 and 6 - 24 with hint 28 to work around certain CN63XXP1 errata.

`-m4010`
`-no-m4010`
  Generate code for the LSI R4010 chip. This tells the assembler to accept the R4010-specific instructions (``addciu'`, ``ffc'`, etc.), and to not schedule ``nop'` instructions around accesses to the ``HI'` and ``LO'` registers. ``-no-m4010'` turns off this option.

`-m4650`
`-no-m4650`
  Generate code for the MIPS R4650 chip. This tells the assembler to accept the ``mad'` and ``madu'` instruction, and to not schedule ``nop'` instructions around accesses to the ``HI'` and ``LO'` registers. ``-no-m4650'` turns off this option.

`-m3900`
`-no-m3900`
`-m4100`
`-no-m4100`
  For each option ``-mnnnn'`, generate code for the MIPS Rnnnn chip. This tells the assembler to accept instructions specific to that chip, and to schedule for that chip's hazards.

`-march=cpu`
  Generate code for a particular MIPS CPU. It is exactly equivalent to ``-mcpu'`, except that there are more value of cpu understood. Valid cpu value are:

  > 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 5kc, 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f, loongson3a, octeon, octeon+, octeon2, xlr, xlp

  For compatibility reasons, ``nx'` and ``bfx'` are accepted as synonyms for ``nf1_1'`. These values are deprecated.

`-mtune=cpu`
  Schedule and tune for a particular MIPS CPU. Valid cpu values are identical to ``-march=cpu'`.

`-mabi=abi`
  Record which ABI the source code uses. The recognized arguments are: ``32'`, ``n32'`, ``o64'`, ``64'` and ``eabi'`.

`-msym32`
`-mno-sym32`
  Equivalent to adding `.set sym32` or `.set nosym32` to the beginning of the assembler input. See section 9.25.3 Directives to override the size of symbols.

`-nocpp`
  This option is ignored. It is accepted for command-line compatibility with other assemblers, which use it to turn off C style preprocessing. With GNU `as`, there is no need for ``-nocpp'`, because the GNU assembler itself never runs the C preprocessor.

`-msoft-float`
`-mhard-float`
  Disable or enable floating-point instructions. Note that by default floating-point instructions are always allowed even with CPU targets that don't have support for these instructions.

`-msingle-float`
`-mdouble-float`
  Disable or enable double-precision floating-point operations. Note that by default double-precision floating-point operations are always allowed even with CPU targets that don't have support for these operations.

`--construct-floats`
`--no-construct-floats`
  The `--no-construct-floats` option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. This feature is useful if the processor support the FR bit in its status register, and this bit is known (by the programmer) to be set. This bit prevents the aliasing of the double width register by the single width registers.

  By default `--construct-floats` is selected, allowing construction of these floating point constants.

`--relax-branch`
`--no-relax-branch`
  The ``--relax-branch'` option enables the relaxation of out-of-range branches. Any branches whose target cannot be reached directly are converted to a small instruction sequence including an inverse-condition branch to the physically next instruction, and a jump to the original target is inserted between the two instructions. In PIC code the jump will involve further instructions for address calculation.

  The `BC1ANY2F`, `BC1ANY2T`, `BC1ANY4F`, `BC1ANY4T`, `BPOSGE32` and `BPOSGE64` instructions are excluded from relaxation, because they have no complementing counterparts. They could be relaxed with the use of a longer sequence involving another branch, however this has not been implemented and if their target turns out of reach, they produce an error even if branch relaxation is enabled.

  Also no MIPS16 branches are ever relaxed.

  By default ``--no-relax-branch'` is selected, causing any out-of-range branches to produce an error.

`-mnan=encoding`
  This option indicates whether the source code uses the IEEE 2008 NaN encoding (``-mnan=2008'`) or the original MIPS encoding (``-mnan=legacy'`). It is equivalent to adding a `.nan` directive to the beginning of the source file. See section 9.25.9 Directives to record which NaN encoding is being used.

  ``-mnan=legacy'` is the default if no ``-mnan'` option or `.nan` directive is used.

`--trap`
`--no-break`
  `as` automatically macro expands certain division and multiplication instructions to check for overflow and division by zero. This option causes `as` to generate code to take a trap exception rather than a break exception when an error is detected. The trap instructions are only supported at Instruction Set Architecture level 2 and higher.

`--break`
`--no-trap`
  Generate code to take a break exception rather than a trap exception when an error is detected. This is the default.

`-mpdr`
`-mno-pdr`
  Control generation of `.pdr` sections. Off by default on IRIX, on elsewhere.

`-mshared`
`-mno-shared`
  When generating code using the Unix calling conventions (selected by ``-KPIC'` or ``-mcall_shared'`), gas will normally generate code which can go into a shared library. The ``-mno-shared'` option tells gas to generate code which uses the calling convention, but can not go into a shared library. The resulting code is slightly more efficient. This option only affects the handling of the ``.cpload'` and ``.cpsetup'` pseudo-ops.

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### 9.25.2 High-level assembly macros

MIPS assemblers have traditionally provided a wider range of instructions than the MIPS architecture itself. These extra instructions are usually referred to as "macro" instructions (2).

Some MIPS macro instructions extend an underlying architectural instruction while others are entirely new. An example of the former type is `and`, which allows the third operand to be either a register or an arbitrary immediate value. Examples of the latter type include `bgt`, which branches to the third operand when the first operand is greater than the second operand, and `ulh`, which implements an unaligned 2-byte load.

One of the most common extensions provided by macros is to expand memory offsets to the full address range (32 or 64 bits) and to allow symbolic offsets such as ``my_data + 4'` to be used in place of integer constants. For example, the architectural instruction `lbu` allows only a signed 16-bit offset, whereas the macro `lbu` allows code such as ``lbu $4,array+32769($5)'`. The implementation of these symbolic offsets depends on several factors, such as whether the assembler is generating SVR4-style PIC (selected by ``-KPIC'`, see section Assembler options), the size of symbols (see section Directives to override the size of symbols), and the small data limit (see section Controlling the use of small data accesses).

Sometimes it is undesirable to have one assembly instruction expand to several machine instructions. The directive `.set nomacro` tells the assembler to warn when this happens. `.set macro` restores the default behavior.

Some macro instructions need a temporary register to store intermediate results. This register is usually `$1`, also known as `$at`, but it can be changed to any core register reg using `.set at=reg`. Note that `$at` always refers to `$1` regardless of which register is being used as the temporary register.

Implicit uses of the temporary register in macros could interfere with explicit uses in the assembly code. The assembler therefore warns whenever it sees an explicit use of the temporary register. The directive `.set noat` silences this warning while `.set at` restores the default behavior. It is safe to use `.set noat` while `.set nomacro` is in effect since single-instruction macros never need a temporary register.

Note that while the GNU assembler provides these macros for compatibility, it does not make any attempt to optimize them with the surrounding code.

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### 9.25.3 Directives to override the size of symbols

The n64 ABI allows symbols to have any 64-bit value. Although this provides a great deal of flexibility, it means that some macros have much longer expansions than their 32-bit counterparts. For example, the non-PIC expansion of ``dla $4,sym'` is usually:

    lui     $4,%highest(sym)
    lui     $1,%hi(sym)
    daddiu  $4,$4,%higher(sym)
    daddiu  $1,$1,%lo(sym)
    dsll32  $4,$4,0
    daddu   $4,$4,$1

whereas the 32-bit expansion is simply:

    lui     $4,%hi(sym)
    daddiu  $4,$4,%lo(sym)

n64 code is sometimes constructed in such a way that all symbolic constants are known to have 32-bit values, and in such cases, it's preferable to use the 32-bit expansion instead of the 64-bit expansion.

You can use the `.set sym32` directive to tell the assembler that, from this point on, all expressions of the form ``symbol'` or ``symbol + offset'` have 32-bit values. For example:

    .set sym32
    dla     $4,sym
    lw      $4,sym+16
    sw      $4,sym+0x8000($4)

will cause the assembler to treat ``sym'`, `sym+16` and `sym+0x8000` as 32-bit values. The handling of non-symbolic addresses is not affected.

The directive `.set nosym32` ends a `.set sym32` block and reverts to the normal behavior. It is also possible to change the symbol size using the command-line options ``-msym32'` and ``-mno-sym32'`.

These options and directives are always accepted, but at present, they have no effect for anything other than n64.

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### 9.25.4 Controlling the use of small data accesses

It often takes several instructions to load the address of a symbol. For example, when ``addr'` is a 32-bit symbol, the non-PIC expansion of ``dla $4,addr'` is usually:

    lui     $4,%hi(addr)
    daddiu  $4,$4,%lo(addr)

The sequence is much longer when ``addr'` is a 64-bit symbol. See section Directives to override the size of symbols.

In order to cut down on this overhead, most embedded MIPS systems set aside a 64-kilobyte "small data" area and guarantee that all data of size n and smaller will be placed in that area. The limit n is passed to both the assembler and the linker using the command-line option ``-G n'`, see section Assembler options. Note that the same value of n must be used when linking and when assembling all input files to the link; any inconsistency could cause a relocation overflow error.

The size of an object in the `.bss` section is set by the `.comm` or `.lcomm` directive that defines it. The size of an external object may be set with the `.extern` directive. For example, ``.extern sym,4'` declares that the object at `sym` is 4 bytes in length, while leaving `sym` otherwise undefined.

When no ``-G'` option is given, the default limit is 8 bytes. The option ``-G 0'` prevents any data from being automatically classified as small.

It is also possible to mark specific objects as small by putting them in the special sections `.sdata` and `.sbss`, which are "small" counterparts of `.data` and `.bss` respectively. The toolchain will treat such data as small regardless of the ``-G'` setting.

On startup, systems that support a small data area are expected to initialize register `$28`, also known as `$gp`, in such a way that small data can be accessed using a 16-bit offset from that register. For example, when ``addr'` is small data, the ``dla $4,addr'` instruction above is equivalent to:

    daddiu  $4,$28,%gp_rel(addr)

Small data is not supported for SVR4-style PIC.

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### 9.25.5 Directives to override the ISA level

GNU `as` supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: `.set mipsn`. n should be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. `.set mipsn` affects not only which instructions are permitted, but also how certain macros are expanded. `.set mips0` restores the ISA level to its original level: either the level you selected with command line options, or the default for your configuration. You can use this feature to permit specific MIPS III instructions while assembling in 32 bit mode. Use this directive with care!

The `.set arch=cpu` directive provides even finer control. It changes the effective CPU target and allows the assembler to use instructions specific to a particular CPU. All CPUs supported by the ``-march'` command line option are also selectable by this directive. The original value is restored by `.set arch=default`.

The directive `.set mips16` puts the assembler into MIPS 16 mode, in which it will assemble instructions for the MIPS 16 processor. Use `.set nomips16` to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

The directive `.set micromips` puts the assembler into microMIPS mode, in which it will assemble instructions for the microMIPS processor. Use `.set nomicromips` to return to normal 32 bit mode.

Traditional MIPS assemblers do not support this directive.

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### 9.25.6 Directives to control code generation

The directive `.set insn32` makes the assembler only use 32-bit instruction encodings when generating code for the microMIPS processor. This directive inhibits the use of any 16-bit instructions from that point on in the assembly. The `.set noinsn32` directive allows 16-bit instructions to be accepted.

Traditional MIPS assemblers do not support this directive.

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### 9.25.7 Directives for extending MIPS 16 bit instructions

By default, MIPS 16 instructions are automatically extended to 32 bits when necessary. The directive `.set noautoextend` will turn this off. When `.set noautoextend` is in effect, any 32 bit instruction must be explicitly extended with the `.e` modifier (e.g., `li.e $4,1000`). The directive `.set autoextend` may be used to once again automatically extend instructions when necessary.

This directive is only meaningful when in MIPS 16 mode. Traditional MIPS assemblers do not support this directive.

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### 9.25.8 Directive to mark data as an instruction

The `.insn` directive tells `as` that the following data is actually instructions. This makes a difference in MIPS 16 and microMIPS modes: when loading the address of a label which precedes instructions, `as` automatically adds 1 to the value, so that jumping to the loaded address will do the right thing.

The `.global` and `.globl` directives supported by `as` will by default mark the symbol as pointing to a region of data not code. This means that, for example, any instructions following such a symbol will not be disassembled by `objdump` as it will regard them as data. To change this behaviour an optional section name can be placed after the symbol name in the `.global` directive. If this section exists and is known to be a code section, then the symbol will be marked as poiting at code not data. Ie the syntax for the directive is:

`.global symbol[ section][, symbol[ section]] ...`,

Here is a short example:

            .global foo .text, bar, baz .data
    foo:
            nop
    bar:
            .word 0x0
    baz:
            .word 0x1

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### 9.25.9 Directives to record which NaN encoding is being used

The IEEE 754 floating-point standard defines two types of not-a-number (NaN) data: "signalling" NaNs and "quiet" NaNs. The original version of the standard did not specify how these two types should be distinguished. Most implementations followed the i387 model, in which the first bit of the significand is set for quiet NaNs and clear for signalling NaNs. However, the original MIPS implementation assigned the opposite meaning to the bit, so that it was set for signalling NaNs and clear for quiet NaNs.

The 2008 revision of the standard formally suggested the i387 choice and as from Sep 2012 the current release of the MIPS architecture therefore optionally supports that form. Code that uses one NaN encoding would usually be incompatible with code that uses the other NaN encoding, so MIPS ELF objects have a flag (`EF_MIPS_NAN2008`) to record which encoding is being used.

Assembly files can use the `.nan` directive to select between the two encodings. ``.nan 2008'` says that the assembly file uses the IEEE 754-2008 encoding while ``.nan legacy'` says that the file uses the original MIPS encoding. If several `.nan` directives are given, the final setting is the one that is used.

The command-line options ``-mnan=legacy'` and ``-mnan=2008'` can be used instead of ``.nan legacy'` and ``.nan 2008'` respectively. However, any `.nan` directive overrides the command-line setting.

``.nan legacy'` is the default if no `.nan` directive or ``-mnan'` option is given.

Note that GNU `as` does not produce NaNs itself and therefore these directives do not affect code generation. They simply control the setting of the `EF_MIPS_NAN2008` flag.

Traditional MIPS assemblers do not support these directives.

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### 9.25.10 Directives to save and restore options

The directives `.set push` and `.set pop` may be used to save and restore the current settings for all the options which are controlled by `.set`. The `.set push` directive saves the current settings on a stack. The `.set pop` directive pops the stack and restores the settings.

These directives can be useful inside an macro which must change an option such as the ISA level or instruction reordering but does not want to change the state of the code which invoked the macro.

Traditional MIPS assemblers do not support these directives.

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### 9.25.11 Directives to control generation of MIPS ASE instructions

The directive `.set mips3d` makes the assembler accept instructions from the MIPS-3D Application Specific Extension from that point on in the assembly. The `.set nomips3d` directive prevents MIPS-3D instructions from being accepted.

The directive `.set smartmips` makes the assembler accept instructions from the SmartMIPS Application Specific Extension to the MIPS32 ISA from that point on in the assembly. The `.set nosmartmips` directive prevents SmartMIPS instructions from being accepted.

The directive `.set mdmx` makes the assembler accept instructions from the MDMX Application Specific Extension from that point on in the assembly. The `.set nomdmx` directive prevents MDMX instructions from being accepted.

The directive `.set dsp` makes the assembler accept instructions from the DSP Release 1 Application Specific Extension from that point on in the assembly. The `.set nodsp` directive prevents DSP Release 1 instructions from being accepted.

The directive `.set dspr2` makes the assembler accept instructions from the DSP Release 2 Application Specific Extension from that point on in the assembly. This dirctive implies `.set dsp`. The `.set nodspr2` directive prevents DSP Release 2 instructions from being accepted.

The directive `.set mt` makes the assembler accept instructions from the MT Application Specific Extension from that point on in the assembly. The `.set nomt` directive prevents MT instructions from being accepted.

The directive `.set mcu` makes the assembler accept instructions from the MCU Application Specific Extension from that point on in the assembly. The `.set nomcu` directive prevents MCU instructions from being accepted.

The directive `.set msa` makes the assembler accept instructions from the MIPS SIMD Architecture Extension from that point on in the assembly. The `.set nomsa` directive prevents MSA instructions from being accepted.

The directive `.set virt` makes the assembler accept instructions from the Virtualization Application Specific Extension from that point on in the assembly. The `.set novirt` directive prevents Virtualization instructions from being accepted.

Traditional MIPS assemblers do not support these directives.

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### 9.25.12 Directives to override floating-point options

The directives `.set softfloat` and `.set hardfloat` provide finer control of disabling and enabling float-point instructions. These directives always override the default (that hard-float instructions are accepted) or the command-line options (``-msoft-float'` and ``-mhard-float'`).

The directives `.set singlefloat` and `.set doublefloat` provide finer control of disabling and enabling double-precision float-point operations. These directives always override the default (that double-precision operations are accepted) or the command-line options (``-msingle-float'` and ``-mdouble-float'`).

Traditional MIPS assemblers do not support these directives.

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### 9.25.13 Syntactical considerations for the MIPS assembler

> 9.25.13.1 Special Characters |  |

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#### 9.25.13.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.26 MMIX Dependent Features

> 9.26.1 Command-line Options |  |
> 9.26.2 Instruction expansion |  |
> 9.26.3 Syntax |  |
> 9.26.4 Differences to `mmixal` |  | Differences to `mmixal` syntax and semantics

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### 9.26.1 Command-line Options

The MMIX version of `as` has some machine-dependent options.

When ``--fixed-special-register-names'` is specified, only the register names specified in 9.26.3.3 Register names are recognized in the instructions `PUT` and `GET`.

You can use the ``--globalize-symbols'` to make all symbols global. This option is useful when splitting up a `mmixal` program into several files.

The ``--gnu-syntax'` turns off most syntax compatibility with `mmixal`. Its usability is currently doubtful.

The ``--relax'` option is not fully supported, but will eventually make the object file prepared for linker relaxation.

If you want to avoid inadvertently calling a predefined symbol and would rather get an error, for example when using `as` with a compiler or other machine-generated code, specify ``--no-predefined-syms'`. This turns off built-in predefined definitions of all such symbols, including rounding-mode symbols, segment symbols, ``BIT'` symbols, and `TRAP` symbols used in `mmix` "system calls". It also turns off predefined special-register names, except when used in `PUT` and `GET` instructions.

By default, some instructions are expanded to fit the size of the operand or an external symbol (see section 9.26.2 Instruction expansion). By passing ``--no-expand'`, no such expansion will be done, instead causing errors at link time if the operand does not fit.

The `mmixal` documentation (see mmixsite) specifies that global registers allocated with the ``GREG'` directive (see MMIX-greg) and initialized to the same non-zero value, will refer to the same global register. This isn't strictly enforceable in `as` since the final addresses aren't known until link-time, but it will do an effort unless the ``--no-merge-gregs'` option is specified. (Register merging isn't yet implemented in `ld`.)

`as` will warn every time it expands an instruction to fit an operand unless the option ``-x'` is specified. It is believed that this behaviour is more useful than just mimicking `mmixal`'s behaviour, in which instructions are only expanded if the ``-x'` option is specified, and assembly fails otherwise, when an instruction needs to be expanded. It needs to be kept in mind that `mmixal` is both an assembler and linker, while `as` will expand instructions that at link stage can be contracted. (Though linker relaxation isn't yet implemented in `ld`.) The option ``-x'` also imples ``--linker-allocated-gregs'`.

If instruction expansion is enabled, `as` can expand a ``PUSHJ'` instruction into a series of instructions. The shortest expansion is to not expand it, but just mark the call as redirectable to a stub, which `ld` creates at link-time, but only if the original ``PUSHJ'` instruction is found not to reach the target. The stub consists of the necessary instructions to form a jump to the target. This happens if `as` can assert that the ``PUSHJ'` instruction can reach such a stub. The option ``--no-pushj-stubs'` disables this shorter expansion, and the longer series of instructions is then created at assembly-time. The option ``--no-stubs'` is a synonym, intended for compatibility with future releases, where generation of stubs for other instructions may be implemented.

Usually a two-operand-expression (see GREG-base) without a matching ``GREG'` directive is treated as an error by `as`. When the option ``--linker-allocated-gregs'` is in effect, they are instead passed through to the linker, which will allocate as many global registers as is needed.

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### 9.26.2 Instruction expansion

When `as` encounters an instruction with an operand that is either not known or does not fit the operand size of the instruction, `as` (and `ld`) will expand the instruction into a sequence of instructions semantically equivalent to the operand fitting the instruction. Expansion will take place for the following instructions:

``GETA'`
  Expands to a sequence of four instructions: `SETL`, `INCML`, `INCMH` and `INCH`. The operand must be a multiple of four.
Conditional branches
  A branch instruction is turned into a branch with the complemented condition and prediction bit over five instructions; four instructions setting `$255` to the operand value, which like with `GETA` must be a multiple of four, and a final `GO $255,$255,0`.
``PUSHJ'`
  Similar to expansion for conditional branches; four instructions set `$255` to the operand value, followed by a `PUSHGO $255,$255,0`.
``JMP'`
  Similar to conditional branches and `PUSHJ`. The final instruction is `GO $255,$255,0`.

The linker `ld` is expected to shrink these expansions for code assembled with ``--relax'` (though not currently implemented).

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### 9.26.3 Syntax

The assembly syntax is supposed to be upward compatible with that described in Sections 1.3 and 1.4 of ``The Art of Computer Programming, Volume 1'`. Draft versions of those chapters as well as other MMIX information is located at http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html. Most code examples from the mmixal package located there should work unmodified when assembled and linked as single files, with a few noteworthy exceptions (see section 9.26.4 Differences to `mmixal`).

Before an instruction is emitted, the current location is aligned to the next four-byte boundary. If a label is defined at the beginning of the line, its value will be the aligned value.

In addition to the traditional hex-prefix ``0x'`, a hexadecimal number can also be specified by the prefix character ``#'`.

After all operands to an MMIX instruction or directive have been specified, the rest of the line is ignored, treated as a comment.

> 9.26.3.1 Special Characters |  |
> 9.26.3.2 Symbols |  |
> 9.26.3.3 Register names |  | Register Names
> 9.26.3.4 Assembler Directives |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.26.3.1 Special Characters

The characters ``*'` and ``#'` are line comment characters; each start a comment at the beginning of a line, but only at the beginning of a line. A ``#'` prefixes a hexadecimal number if found elsewhere on a line. If a ``#'` appears at the start of a line the whole line is treated as a comment, but the line can also act as a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Two other characters, ``%'` and ``!'`, each start a comment anywhere on the line. Thus you can't use the ``modulus'` and ``not'` operators in expressions normally associated with these two characters.

A ``;'` is a line separator, treated as a new-line, so separate instructions can be specified on a single line.

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#### 9.26.3.2 Symbols

The character ``:'` is permitted in identifiers. There are two exceptions to it being treated as any other symbol character: if a symbol begins with ``:'`, it means that the symbol is in the global namespace and that the current prefix should not be prepended to that symbol (see MMIX-prefix). The ``:'` is then not considered part of the symbol. For a symbol in the label position (first on a line), a ``:'` at the end of a symbol is silently stripped off. A label is permitted, but not required, to be followed by a ``:'`, as with many other assembly formats.

The character ``@'` in an expression, is a synonym for ``.'`, the current location.

In addition to the common forward and backward local symbol formats (see section 5.3 Symbol Names), they can be specified with upper-case ``B'` and ``F'`, as in ``8B'` and ``9F'`. A local label defined for the current position is written with a ``H'` appended to the number:

    3H LDB $0,$1,2

This and traditional local-label formats cannot be mixed: a label must be defined and referred to using the same format.

There's a minor caveat: just as for the ordinary local symbols, the local symbols are translated into ordinary symbols using control characters are to hide the ordinal number of the symbol. Unfortunately, these symbols are not translated back in error messages. Thus you may see confusing error messages when local symbols are used. Control characters ``\003'` (control-C) and ``\004'` (control-D) are used for the MMIX-specific local-symbol syntax.

The symbol ``Main'` is handled specially; it is always global.

By defining the symbols ``__.MMIX.start..text'` and ``__.MMIX.start..data'`, the address of respectively the ``.text'` and ``.data'` segments of the final program can be defined, though when linking more than one object file, the code or data in the object file containing the symbol is not guaranteed to be start at that position; just the final executable. See MMIX-loc.

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#### 9.26.3.3 Register names

Local and global registers are specified as ``$0'` to ``$255'`. The recognized special register names are ``rJ'`, ``rA'`, ``rB'`, ``rC'`, ``rD'`, ``rE'`, ``rF'`, ``rG'`, ``rH'`, ``rI'`, ``rK'`, ``rL'`, ``rM'`, ``rN'`, ``rO'`, ``rP'`, ``rQ'`, ``rR'`, ``rS'`, ``rT'`, ``rU'`, ``rV'`, ``rW'`, ``rX'`, ``rY'`, ``rZ'`, ``rBB'`, ``rTT'`, ``rWW'`, ``rXX'`, ``rYY'` and ``rZZ'`. A leading ``:'` is optional for special register names.

Local and global symbols can be equated to register names and used in place of ordinary registers.

Similarly for special registers, local and global symbols can be used. Also, symbols equated from numbers and constant expressions are allowed in place of a special register, except when either of the options `--no-predefined-syms` and `--fixed-special-register-names` are specified. Then only the special register names above are allowed for the instructions having a special register operand; `GET` and `PUT`.

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#### 9.26.3.4 Assembler Directives

`LOC`

  The `LOC` directive sets the current location to the value of the operand field, which may include changing sections. If the operand is a constant, the section is set to either `.data` if the value is `0x2000000000000000` or larger, else it is set to `.text`. Within a section, the current location may only be changed to monotonically higher addresses. A LOC expression must be a previously defined symbol or a "pure" constant.

  An example, which sets the label prev to the current location, and updates the current location to eight bytes forward:

      prev LOC @+8

  When a LOC has a constant as its operand, a symbol `__.MMIX.start..text` or `__.MMIX.start..data` is defined depending on the address as mentioned above. Each such symbol is interpreted as special by the linker, locating the section at that address. Note that if multiple files are linked, the first object file with that section will be mapped to that address (not necessarily the file with the LOC definition).

`LOCAL`

  Example:

       LOCAL external_symbol
       LOCAL 42
       .local asymbol

  This directive-operation generates a link-time assertion that the operand does not correspond to a global register. The operand is an expression that at link-time resolves to a register symbol or a number. A number is treated as the register having that number. There is one restriction on the use of this directive: the pseudo-directive must be placed in a section with contents, code or data.

`IS`

  The `IS` directive:

      asymbol IS an_expression

  sets the symbol ``asymbol'` to ``an_expression'`. A symbol may not be set more than once using this directive. Local labels may be set using this directive, for example:

      5H IS @+4

`GREG`

  This directive reserves a global register, gives it an initial value and optionally gives it a symbolic name. Some examples:

      areg GREG
      breg GREG data_value
           GREG data_buffer
           .greg creg, another_data_value

  The symbolic register name can be used in place of a (non-special) register. If a value isn't provided, it defaults to zero. Unless the option ``--no-merge-gregs'` is specified, non-zero registers allocated with this directive may be eliminated by `as`; another register with the same value used in its place. Any of the instructions ``CSWAP'`, ``GO'`, ``LDA'`, ``LDBU'`, ``LDB'`, ``LDHT'`, ``LDOU'`, ``LDO'`, ``LDSF'`, ``LDTU'`, ``LDT'`, ``LDUNC'`, ``LDVTS'`, ``LDWU'`, ``LDW'`, ``PREGO'`, ``PRELD'`, ``PREST'`, ``PUSHGO'`, ``STBU'`, ``STB'`, ``STCO'`, ``STHT'`, ``STOU'`, ``STSF'`, ``STTU'`, ``STT'`, ``STUNC'`, ``SYNCD'`, ``SYNCID'`, can have a value nearby an initial value in place of its second and third operands. Here, "nearby" is defined as within the range 0...255 from the initial value of such an allocated register.

      buffer1 BYTE 0,0,0,0,0
      buffer2 BYTE 0,0,0,0,0
       ...
       GREG buffer1
       LDOU $42,buffer2

  In the example above, the ``Y'` field of the `LDOUI` instruction (LDOU with a constant Z) will be replaced with the global register allocated for ``buffer1'`, and the ``Z'` field will have the value 5, the offset from ``buffer1'` to ``buffer2'`. The result is equivalent to this code:

      buffer1 BYTE 0,0,0,0,0
      buffer2 BYTE 0,0,0,0,0
       ...
      tmpreg GREG buffer1
       LDOU $42,tmpreg,(buffer2-buffer1)

  Global registers allocated with this directive are allocated in order higher-to-lower within a file. Other than that, the exact order of register allocation and elimination is undefined. For example, the order is undefined when more than one file with such directives are linked together. With the options ``-x'` and ``--linker-allocated-gregs'`, ``GREG'` directives for two-operand cases like the one mentioned above can be omitted. Sufficient global registers will then be allocated by the linker.

`BYTE`

  The ``BYTE'` directive takes a series of operands separated by a comma. If an operand is a string (see section 3.6.1.1 Strings), each character of that string is emitted as a byte. Other operands must be constant expressions without forward references, in the range 0...255. If you need operands having expressions with forward references, use ``.byte'` (see section 7.10 `.byte expressions`). An operand can be omitted, defaulting to a zero value.

`WYDE`
`TETRA`
`OCTA`

  The directives ``WYDE'`, ``TETRA'` and ``OCTA'` emit constants of two, four and eight bytes size respectively. Before anything else happens for the directive, the current location is aligned to the respective constant-size boundary. If a label is defined at the beginning of the line, its value will be that after the alignment. A single operand can be omitted, defaulting to a zero value emitted for the directive. Operands can be expressed as strings (see section 3.6.1.1 Strings), in which case each character in the string is emitted as a separate constant of the size indicated by the directive.

`PREFIX`

  The ``PREFIX'` directive sets a symbol name prefix to be prepended to all symbols (except local symbols, see section 9.26.3.2 Symbols), that are not prefixed with ``:'`, until the next ``PREFIX'` directive. Such prefixes accumulate. For example,

       PREFIX a
       PREFIX b
      c IS 0

  defines a symbol ``abc'` with the value 0.

`BSPEC`
`ESPEC`

  A pair of ``BSPEC'` and ``ESPEC'` directives delimit a section of special contents (without specified semantics). Example:

       BSPEC 42
       TETRA 1,2,3
       ESPEC

  The single operand to ``BSPEC'` must be number in the range 0...255. The ``BSPEC'` number 80 is used by the GNU binutils implementation.

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### 9.26.4 Differences to `mmixal`

The binutils `as` and `ld` combination has a few differences in function compared to `mmixal` (see mmixsite).

The replacement of a symbol with a GREG-allocated register (see GREG-base) is not handled the exactly same way in `as` as in `mmixal`. This is apparent in the `mmixal` example file `inout.mms`, where different registers with different offsets, eventually yielding the same address, are used in the first instruction. This type of difference should however not affect the function of any program unless it has specific assumptions about the allocated register number.

Line numbers (in the ``mmo'` object format) are currently not supported.

Expression operator precedence is not that of mmixal: operator precedence is that of the C programming language. It's recommended to use parentheses to explicitly specify wanted operator precedence whenever more than one type of operators are used.

The serialize unary operator `&`, the fractional division operator ``//'`, the logical not operator `!` and the modulus operator ``%'` are not available.

Symbols are not global by default, unless the option ``--globalize-symbols'` is passed. Use the ``.global'` directive to globalize symbols (see section 7.57 `.global symbol`, `.globl symbol`).

Operand syntax is a bit stricter with `as` than `mmixal`. For example, you can't say `addu 1,2,3`, instead you must write `addu $1,$2,3`.

You can't LOC to a lower address than those already visited (i.e., "backwards").

A LOC directive must come before any emitted code.

Predefined symbols are visible as file-local symbols after use. (In the ELF file, that is--the linked mmo file has no notion of a file-local symbol.)

Some mapping of constant expressions to sections in LOC expressions is attempted, but that functionality is easily confused and should be avoided unless compatibility with `mmixal` is required. A LOC expression to ``0x2000000000000000'` or higher, maps to the ``.data'` section and lower addresses map to the ``.text'` section (see MMIX-loc).

The code and data areas are each contiguous. Sparse programs with far-away LOC directives will take up the same amount of space as a contiguous program with zeros filled in the gaps between the LOC directives. If you need sparse programs, you might try and get the wanted effect with a linker script and splitting up the code parts into sections (see section 7.99 `.section name`). Assembly code for this, to be compatible with `mmixal`, would look something like:

     .if 0
     LOC away_expression
     .else
     .section away,"ax"
     .fi

`as` will not execute the LOC directive and `mmixal` ignores the lines with `.`. This construct can be used generally to help compatibility.

Symbols can't be defined twice--not even to the same value.

Instruction mnemonics are recognized case-insensitive, though the ``IS'` and ``GREG'` pseudo-operations must be specified in upper-case characters.

There's no unicode support.

The following is a list of programs in ``mmix.tar.gz'`, available at http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html, last checked with the version dated 2001-08-25 (md5sum c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal` but do not assemble with `as`:

`silly.mms`
  LOC to a previous address.
`sim.mms`
  Redefines symbol ``Done'`.
`test.mms`
  Uses the serial operator ``&'`.

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## 9.27 MSP 430 Dependent Features

> 9.27.1 Options |  |
> 9.27.2 Syntax |  |
> 9.27.3 Floating Point |  |
> 9.27.4 MSP 430 Machine Directives |  |
> 9.27.5 Opcodes |  |
> 9.27.6 Profiling Capability |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.27.1 Options

`-mmcu`
  selects the mpu arch. If the architecture is 430Xv2 then this also enables NOP generation unless the ``-mN'` is also specified.

`-mcpu`
  selects the cpu architecture. If the architecture is 430Xv2 then this also enables NOP generation unless the ``-mN'` is also specified.

`-mP`
  enables polymorph instructions handler.

`-mQ`
  enables relaxation at assembly time. DANGEROUS!

`-ml`
  indicates that the input uses the large code model.

`-mN`
  disables the generation of a NOP instruction following any instruction that might change the interrupts enabled/disabled state. For the 430Xv2 architecture the instructions: `EINT`, `DINT`, `BIC #8, SR`, `BIS #8, SR` and `MOV.W <>, SR` must be followed by a NOP instruction in order to ensure the correct processing of interrupts. By default generation of the NOP instruction happens automatically, but this command line option disables this behaviour. It is then up to the programmer to ensure that interrupts are enabled and disabled correctly.

`-md`
  mark the object file as one that requires data to copied from ROM to RAM at execution startup. Disabled by default.

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### 9.27.2 Syntax

> 9.27.2.1 Macros |  |
> 9.27.2.2 Special Characters |  |
> 9.27.2.3 Register Names |  |
> 9.27.2.4 Assembler Extensions |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.27.2.1 Macros

The macro syntax used on the MSP 430 is like that described in the MSP 430 Family Assembler Specification. Normal `as` macros should still work.

Additional built-in macros are:

`llo(exp)`
  Extracts least significant word from 32-bit expression 'exp'.

`lhi(exp)`
  Extracts most significant word from 32-bit expression 'exp'.

`hlo(exp)`
  Extracts 3rd word from 64-bit expression 'exp'.

`hhi(exp)`
  Extracts 4rd word from 64-bit expression 'exp'.

They normally being used as an immediate source operand.

        mov	#llo(1), r10	;	== mov	#1, r10
        mov	#lhi(1), r10	;	== mov	#0, r10

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#### 9.27.2.2 Special Characters

A semicolon (``;'`) appearing anywhere on a line starts a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but it can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Multiple statements can appear on the same line provided that they are separated by the ``{'` character.

The character ``$'` in jump instructions indicates current location and implemented only for TI syntax compatibility.

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#### 9.27.2.3 Register Names

General-purpose registers are represented by predefined symbols of the form ``rN'` (for global registers), where N represents a number between `0` and `15`. The leading letters may be in either upper or lower case; for example, ``r13'` and ``R7'` are both valid register names.

Register names ``PC'`, ``SP'` and ``SR'` cannot be used as register names and will be treated as variables. Use ``r0'`, ``r1'`, and ``r2'` instead.

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#### 9.27.2.4 Assembler Extensions

`@rN`
  As destination operand being treated as ``0(rn)'`

`0(rN)`
  As source operand being treated as ``@rn'`

`jCOND +N`
  Skips next N bytes followed by jump instruction and equivalent to ``jCOND $+N+2'`

Also, there are some instructions, which cannot be found in other assemblers. These are branch instructions, which has different opcodes upon jump distance. They all got PC relative addressing mode.

`beq label`
  A polymorph instruction which is ``jeq label'` in case if jump distance within allowed range for cpu's jump instruction. If not, this unrolls into a sequence of

        jne $+6
        br  label

`bne label`
  A polymorph instruction which is ``jne label'` or ``jeq +4; br label'`

`blt label`
  A polymorph instruction which is ``jl label'` or ``jge +4; br label'`

`bltn label`
  A polymorph instruction which is ``jn label'` or ``jn +2; jmp +4; br label'`

`bltu label`
  A polymorph instruction which is ``jlo label'` or ``jhs +2; br label'`

`bge label`
  A polymorph instruction which is ``jge label'` or ``jl +4; br label'`

`bgeu label`
  A polymorph instruction which is ``jhs label'` or ``jlo +4; br label'`

`bgt label`
  A polymorph instruction which is ``jeq +2; jge label'` or ``jeq +6; jl +4; br label'`

`bgtu label`
  A polymorph instruction which is ``jeq +2; jhs label'` or ``jeq +6; jlo +4; br label'`

`bleu label`
  A polymorph instruction which is ``jeq label; jlo label'` or ``jeq +2; jhs +4; br label'`

`ble label`
  A polymorph instruction which is ``jeq label; jl label'` or ``jeq +2; jge +4; br label'`

`jump label`
  A polymorph instruction which is ``jmp label'` or ``br label'`

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.27.3 Floating Point

The MSP 430 family uses IEEE 32-bit floating-point numbers.

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### 9.27.4 MSP 430 Machine Directives

`.file`
  This directive is ignored; it is accepted for compatibility with other MSP 430 assemblers.

  > Warning: in other versions of the GNU assembler, `.file` is used for the directive called `.app-file` in the MSP 430 support.

`.line`
  This directive is ignored; it is accepted for compatibility with other MSP 430 assemblers.

`.arch`
  Sets the target microcontroller in the same way as the ``-mmcu'` command line option.

`.cpu`
  Sets the target architecture in the same way as the ``-mcpu'` command line option.

`.profiler`
  This directive instructs assembler to add new profile entry to the object file.

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### 9.27.5 Opcodes

`as` implements all the standard MSP 430 opcodes. No additional pseudo-instructions are needed on this family.

For information on the 430 machine instruction set, see MSP430 User's Manual, document slau049d, Texas Instrument, Inc.

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### 9.27.6 Profiling Capability

It is a performance hit to use gcc's profiling approach for this tiny target. Even more -- jtag hardware facility does not perform any profiling functions. However we've got gdb's built-in simulator where we can do anything.

We define new section ``.profiler'` which holds all profiling information. We define new pseudo operation ``.profiler'` which will instruct assembler to add new profile entry to the object file. Profile should take place at the present address.

Pseudo operation format:

``.profiler flags,function_to_profile [, cycle_corrector, extra]'`

where:

``flags'` is a combination of the following characters:
`s`
  function entry
`x`
  function exit
`i`
  function is in init section
`f`
  function is in fini section
`l`
  library call
`c`
  libc standard call
`d`
  stack value demand
`I`
  interrupt service routine
`P`
  prologue start
`p`
  prologue end
`E`
  epilogue start
`e`
  epilogue end
`j`
  long jump / sjlj unwind
`a`
  an arbitrary code fragment
`t`
  extra parameter saved (a constant value like frame size)

`function_to_profile`
  a function address
`cycle_corrector`
  a value which should be added to the cycle counter, zero if omitted.
`extra`
  any extra parameter, zero if omitted.

For example:

    .global fxx
    .type fxx,@function
    fxx:
    .LFrameOffset_fxx=0x08
    .profiler "scdP", fxx     ; function entry.
    			  ; we also demand stack value to be saved
      push r11
      push r10
      push r9
      push r8
    .profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
    					  ; (this is a prologue end)
    					  ; note, that spare var filled with
    					  ; the farme size
      mov r15,r8
    ...
    .profiler cdE,fxx         ; check stack
      pop r8
      pop r9
      pop r10
      pop r11
    .profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
      ret                     ; cause 'ret' insn takes 3 cycles

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## 9.28 NS32K Dependent Features

> 9.28.1 Syntax |  |

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### 9.28.1 Syntax

> 9.28.1.1 Special Characters |  |

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#### 9.28.1.1 Special Characters

The presence of a ``#'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

If Sequent compatibility has been configured into the assembler then the ``|'` character appearing as the first character on a line will also indicate the start of a line comment.

The ``;'` character can be used to separate statements on the same line.

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## 9.29 PDP-11 Dependent Features

> 9.29.1 Options |  |
> 9.29.2 Assembler Directives |  |
> 9.29.3 PDP-11 Assembly Language Syntax |  | DEC Syntax versus BSD Syntax
> 9.29.4 Instruction Naming |  |
> 9.29.5 Synthetic Instructions |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.29.1 Options

The PDP-11 version of `as` has a rich set of machine dependent options.

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#### 9.29.1.1 Code Generation Options

`-mpic | -mno-pic`
  Generate position-independent (or position-dependent) code.

  The default is to generate position-independent code.

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#### 9.29.1.2 Instruction Set Extension Options

These options enables or disables the use of extensions over the base line instruction set as introduced by the first PDP-11 CPU: the KA11. Most options come in two variants: a `-m`extension that enables extension, and a `-mno-`extension that disables extension.

The default is to enable all extensions.

`-mall | -mall-extensions`
  Enable all instruction set extensions.

`-mno-extensions`
  Disable all instruction set extensions.

`-mcis | -mno-cis`
  Enable (or disable) the use of the commercial instruction set, which consists of these instructions: `ADDNI`, `ADDN`, `ADDPI`, `ADDP`, `ASHNI`, `ASHN`, `ASHPI`, `ASHP`, `CMPCI`, `CMPC`, `CMPNI`, `CMPN`, `CMPPI`, `CMPP`, `CVTLNI`, `CVTLN`, `CVTLPI`, `CVTLP`, `CVTNLI`, `CVTNL`, `CVTNPI`, `CVTNP`, `CVTPLI`, `CVTPL`, `CVTPNI`, `CVTPN`, `DIVPI`, `DIVP`, `L2DR`, `L3DR`, `LOCCI`, `LOCC`, `MATCI`, `MATC`, `MOVCI`, `MOVC`, `MOVRCI`, `MOVRC`, `MOVTCI`, `MOVTC`, `MULPI`, `MULP`, `SCANCI`, `SCANC`, `SKPCI`, `SKPC`, `SPANCI`, `SPANC`, `SUBNI`, `SUBN`, `SUBPI`, and `SUBP`.

`-mcsm | -mno-csm`
  Enable (or disable) the use of the `CSM` instruction.

`-meis | -mno-eis`
  Enable (or disable) the use of the extended instruction set, which consists of these instructions: `ASHC`, `ASH`, `DIV`, `MARK`, `MUL`, `RTT`, `SOB` `SXT`, and `XOR`.

`-mfis | -mkev11`
`-mno-fis | -mno-kev11`
  Enable (or disable) the use of the KEV11 floating-point instructions: `FADD`, `FDIV`, `FMUL`, and `FSUB`.

`-mfpp | -mfpu | -mfp-11`
`-mno-fpp | -mno-fpu | -mno-fp-11`
  Enable (or disable) the use of FP-11 floating-point instructions: `ABSF`, `ADDF`, `CFCC`, `CLRF`, `CMPF`, `DIVF`, `LDCFF`, `LDCIF`, `LDEXP`, `LDF`, `LDFPS`, `MODF`, `MULF`, `NEGF`, `SETD`, `SETF`, `SETI`, `SETL`, `STCFF`, `STCFI`, `STEXP`, `STF`, `STFPS`, `STST`, `SUBF`, and `TSTF`.

`-mlimited-eis | -mno-limited-eis`
  Enable (or disable) the use of the limited extended instruction set: `MARK`, `RTT`, `SOB`, `SXT`, and `XOR`.

  The -mno-limited-eis options also implies -mno-eis.

`-mmfpt | -mno-mfpt`
  Enable (or disable) the use of the `MFPT` instruction.

`-mmultiproc | -mno-multiproc`
  Enable (or disable) the use of multiprocessor instructions: `TSTSET` and `WRTLCK`.

`-mmxps | -mno-mxps`
  Enable (or disable) the use of the `MFPS` and `MTPS` instructions.

`-mspl | -mno-spl`
  Enable (or disable) the use of the `SPL` instruction.

  Enable (or disable) the use of the microcode instructions: `LDUB`, `MED`, and `XFC`.

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#### 9.29.1.3 CPU Model Options

These options enable the instruction set extensions supported by a particular CPU, and disables all other extensions.

`-mka11`
  KA11 CPU. Base line instruction set only.

`-mkb11`
  KB11 CPU. Enable extended instruction set and `SPL`.

`-mkd11a`
  KD11-A CPU. Enable limited extended instruction set.

`-mkd11b`
  KD11-B CPU. Base line instruction set only.

`-mkd11d`
  KD11-D CPU. Base line instruction set only.

`-mkd11e`
  KD11-E CPU. Enable extended instruction set, `MFPS`, and `MTPS`.

`-mkd11f | -mkd11h | -mkd11q`
  KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set, `MFPS`, and `MTPS`.

`-mkd11k`
  KD11-K CPU. Enable extended instruction set, `LDUB`, `MED`, `MFPS`, `MFPT`, `MTPS`, and `XFC`.

`-mkd11z`
  KD11-Z CPU. Enable extended instruction set, `CSM`, `MFPS`, `MFPT`, `MTPS`, and `SPL`.

`-mf11`
  F11 CPU. Enable extended instruction set, `MFPS`, `MFPT`, and `MTPS`.

`-mj11`
  J11 CPU. Enable extended instruction set, `CSM`, `MFPS`, `MFPT`, `MTPS`, `SPL`, `TSTSET`, and `WRTLCK`.

`-mt11`
  T11 CPU. Enable limited extended instruction set, `MFPS`, and `MTPS`.

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#### 9.29.1.4 Machine Model Options

These options enable the instruction set extensions supported by a particular machine model, and disables all other extensions.

`-m11/03`
  Same as `-mkd11f`.

`-m11/04`
  Same as `-mkd11d`.

`-m11/05 | -m11/10`
  Same as `-mkd11b`.

`-m11/15 | -m11/20`
  Same as `-mka11`.

`-m11/21`
  Same as `-mt11`.

`-m11/23 | -m11/24`
  Same as `-mf11`.

`-m11/34`
  Same as `-mkd11e`.

`-m11/34a`
  Ame as `-mkd11e` `-mfpp`.

`-m11/35 | -m11/40`
  Same as `-mkd11a`.

`-m11/44`
  Same as `-mkd11z`.

`-m11/45 | -m11/50 | -m11/55 | -m11/70`
  Same as `-mkb11`.

`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94`
  Same as `-mj11`.

`-m11/60`
  Same as `-mkd11k`.

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### 9.29.2 Assembler Directives

The PDP-11 version of `as` has a few machine dependent assembler directives.

`.bss`
  Switch to the `bss` section.

`.even`
  Align the location counter to an even number.

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### 9.29.3 PDP-11 Assembly Language Syntax

`as` supports both DEC syntax and BSD syntax. The only difference is that in DEC syntax, a `#` character is used to denote an immediate constants, while in BSD syntax the character for this purpose is `$`.

general-purpose registers are named `r0` through `r7`. Mnemonic alternatives for `r6` and `r7` are `sp` and `pc`, respectively.

Floating-point registers are named `ac0` through `ac3`, or alternatively `fr0` through `fr3`.

Comments are started with a `#` or a `/` character, and extend to the end of the line. (FIXME: clash with immediates?)

Multiple statements on the same line can be separated by the ``;'` character.

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### 9.29.4 Instruction Naming

Some instructions have alternative names.

`BCC`
  `BHIS`

`BCS`
  `BLO`

`L2DR`
  `L2D`

`L3DR`
  `L3D`

`SYS`
  `TRAP`

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### 9.29.5 Synthetic Instructions

The `JBR` and `J`CC synthetic instructions are not supported yet.

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## 9.30 picoJava Dependent Features

> 9.30.1 Options |  |
> 9.30.2 PJ Syntax |  |

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### 9.30.1 Options

`as` has two additional command-line options for the picoJava architecture.

`-ml`
  This option selects little endian data output.

`-mb`
  This option selects big endian data output.

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### 9.30.2 PJ Syntax

> 9.30.2.1 Special Characters |  |

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#### 9.30.2.1 Special Characters

The presence of a ``!'` or ``/'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.31 PowerPC Dependent Features

> 9.31.1 Options |  |
> 9.31.2 PowerPC Assembler Directives |  |
> 9.31.3 PowerPC Syntax |  |

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### 9.31.1 Options

The PowerPC chip family includes several successive levels, using the same core instruction set, but including a few additional instructions at each level. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

The following table lists all available PowerPC options.

`-a32`
  Generate ELF32 or XCOFF32.

`-a64`
  Generate ELF64 or XCOFF64.

`-K PIC`
  Set EF_PPC_RELOCATABLE_LIB in ELF flags.

`-mpwrx | -mpwr2`
  Generate code for POWER/2 (RIOS2).

`-mpwr`
  Generate code for POWER (RIOS1)

`-m601`
  Generate code for PowerPC 601.

`-mppc, -mppc32, -m603, -m604`
  Generate code for PowerPC 603/604.

`-m403, -m405`
  Generate code for PowerPC 403/405.

`-m440`
  Generate code for PowerPC 440. BookE and some 405 instructions.

`-m464`
  Generate code for PowerPC 464.

`-m476`
  Generate code for PowerPC 476.

`-m7400, -m7410, -m7450, -m7455`
  Generate code for PowerPC 7400/7410/7450/7455.

`-m750cl`
  Generate code for PowerPC 750CL.

`-mppc64, -m620`
  Generate code for PowerPC 620/625/630.

`-me500, -me500x2`
  Generate code for Motorola e500 core complex.

`-me500mc`
  Generate code for Freescale e500mc core complex.

`-me500mc64`
  Generate code for Freescale e500mc64 core complex.

`-me5500`
  Generate code for Freescale e5500 core complex.

`-me6500`
  Generate code for Freescale e6500 core complex.

`-mspe`
  Generate code for Motorola SPE instructions.

`-mtitan`
  Generate code for AppliedMicro Titan core complex.

`-mppc64bridge`
  Generate code for PowerPC 64, including bridge insns.

`-mbooke`
  Generate code for 32-bit BookE.

`-ma2`
  Generate code for A2 architecture.

`-me300`
  Generate code for PowerPC e300 family.

`-maltivec`
  Generate code for processors with AltiVec instructions.

`-mvle`
  Generate code for Freescale PowerPC VLE instructions.

`-mvsx`
  Generate code for processors with Vector-Scalar (VSX) instructions.

`-mhtm`
  Generate code for processors with Hardware Transactional Memory instructions.

`-mpower4, -mpwr4`
  Generate code for Power4 architecture.

`-mpower5, -mpwr5, -mpwr5x`
  Generate code for Power5 architecture.

`-mpower6, -mpwr6`
  Generate code for Power6 architecture.

`-mpower7, -mpwr7`
  Generate code for Power7 architecture.

`-mpower8, -mpwr8`
  Generate code for Power8 architecture.

`-mcell`
`-mcell`
  Generate code for Cell Broadband Engine architecture.

`-mcom`
  Generate code Power/PowerPC common instructions.

`-many`
  Generate code for any architecture (PWR/PWRX/PPC).

`-mregnames`
  Allow symbolic names for registers.

`-mno-regnames`
  Do not allow symbolic names for registers.

`-mrelocatable`
  Support for GCC's -mrelocatable option.

`-mrelocatable-lib`
  Support for GCC's -mrelocatable-lib option.

`-memb`
  Set PPC_EMB bit in ELF flags.

`-mlittle, -mlittle-endian, -le`
  Generate code for a little endian machine.

`-mbig, -mbig-endian, -be`
  Generate code for a big endian machine.

`-msolaris`
  Generate code for Solaris.

`-mno-solaris`
  Do not generate code for Solaris.

`-nops=count`
  If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops.

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### 9.31.2 PowerPC Assembler Directives

A number of assembler directives are available for PowerPC. The following table is far from complete.

`.machine "string"`
  This directive allows you to change the machine for which code is generated. `"string"` may be any of the -m cpu selection options (without the -m) enclosed in double quotes, `"push"`, or `"pop"`. `.machine "push"` saves the currently selected cpu, which may be restored with `.machine "pop"`.

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### 9.31.3 PowerPC Syntax

> 9.31.3.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.31.3.1 Special Characters

The presence of a ``#'` on a line indicates the start of a comment that extends to the end of the current line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

If the assembler has been configured for the ppc-*-solaris* target then the ``!'` character also acts as a line comment character. This can be disabled via the ``-mno-solaris'` command line option.

The ``;'` character can be used to separate statements on the same line.

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## 9.32 RL78 Dependent Features

> 9.32.1 RL78 Options |  | RL78 Assembler Command Line Options
> 9.32.2 Symbolic Operand Modifiers |  |
> 9.32.3 Assembler Directives |  |
> 9.32.4 Syntax for the RL78 |  | Syntax

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.32.1 RL78 Options

`relax`
  Enable support for link-time relaxation.

`mg10`
  Mark the generated binary as targeting the G10 variant of the RL78 architecture.

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### 9.32.2 Symbolic Operand Modifiers

The RL78 has three modifiers that adjust the relocations used by the linker:

`%lo16()`

  When loading a 20-bit (or wider) address into registers, this modifier selects the 16 least significant bits.

        movw ax,#%lo16(_sym)

`%hi16()`

  When loading a 20-bit (or wider) address into registers, this modifier selects the 16 most significant bits.

        movw ax,#%hi16(_sym)

`%hi8()`

  When loading a 20-bit (or wider) address into registers, this modifier selects the 8 bits that would go into CS or ES (i.e. bits 23..16).

        mov es, #%hi8(_sym)

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### 9.32.3 Assembler Directives

In addition to the common directives, the RL78 adds these:

`.double`
  Output a constant in "double" format, which is a 32-bit floating point value on RL78.

`.bss`
  Select the BSS section.

`.3byte`
  Output a constant value in a three byte format.

`.int`
`.word`
  Output a constant value in a four byte format.

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### 9.32.4 Syntax for the RL78

> 9.32.4.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.32.4.1 Special Characters

The presence of a ``;'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``|'` character can be used to separate statements on the same line.

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## 9.33 RX Dependent Features

> 9.33.1 RX Options |  | RX Assembler Command Line Options
> 9.33.2 Symbolic Operand Modifiers |  |
> 9.33.3 Assembler Directives |  |
> 9.33.4 Floating Point |  |
> 9.33.5 Syntax for the RX |  | Syntax

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.33.1 RX Options

The Renesas RX port of `as` has a few target specfic command line options:

`-m32bit-doubles`
  This option controls the ABI and indicates to use a 32-bit float ABI. It has no effect on the assembled instructions, but it does influence the behaviour of the ``.double'` pseudo-op. This is the default.

`-m64bit-doubles`
  This option controls the ABI and indicates to use a 64-bit float ABI. It has no effect on the assembled instructions, but it does influence the behaviour of the ``.double'` pseudo-op.

`-mbig-endian`
  This option controls the ABI and indicates to use a big-endian data ABI. It has no effect on the assembled instructions, but it does influence the behaviour of the ``.short'`, ``.hword'`, ``.int'`, ``.word'`, ``.long'`, ``.quad'` and ``.octa'` pseudo-ops.

`-mlittle-endian`
  This option controls the ABI and indicates to use a little-endian data ABI. It has no effect on the assembled instructions, but it does influence the behaviour of the ``.short'`, ``.hword'`, ``.int'`, ``.word'`, ``.long'`, ``.quad'` and ``.octa'` pseudo-ops. This is the default.

`-muse-conventional-section-names`
  This option controls the default names given to the code (.text), initialised data (.data) and uninitialised data sections (.bss).

`-muse-renesas-section-names`
  This option controls the default names given to the code (.P), initialised data (.D_1) and uninitialised data sections (.B_1). This is the default.

`-msmall-data-limit`
  This option tells the assembler that the small data limit feature of the RX port of GCC is being used. This results in the assembler generating an undefined reference to a symbol called `__gp` for use by the relocations that are needed to support the small data limit feature. This option is not enabled by default as it would otherwise pollute the symbol table.

`-mpid`
  This option tells the assembler that the position independent data of the RX port of GCC is being used. This results in the assembler generating an undefined reference to a symbol called `__pid_base`, and also setting the RX_PID flag bit in the e_flags field of the ELF header of the object file.

`-mint-register=num`
  This option tells the assembler how many registers have been reserved for use by interrupt handlers. This is needed in order to compute the correct values for the `%gpreg` and `%pidreg` meta registers.

`-mgcc-abi`
  This option tells the assembler that the old GCC ABI is being used by the assembled code. With this version of the ABI function arguments that are passed on the stack are aligned to a 32-bit boundary.

`-mrx-abi`
  This option tells the assembler that the official RX ABI is being used by the assembled code. With this version of the ABI function arguments that are passed on the stack are aligned to their natural alignments. This option is the default.

`-mcpu=name`
  This option tells the assembler the target CPU type. Currently the `rx200`, `rx600` and `rx610` are recognised as valid cpu names. Attempting to assemble an instruction not supported by the indicated cpu type will result in an error message being generated.

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### 9.33.2 Symbolic Operand Modifiers

The assembler supports one modifier when using symbol addresses in RX instruction operands. The general syntax is the following:

    %gp(symbol)

The modifier returns the offset from the __gp symbol to the specified symbol as a 16-bit value. The intent is that this offset should be used in a register+offset move instruction when generating references to small data. Ie, like this:

      mov.W	 %gp(_foo)[%gpreg], r1

The assembler also supports two meta register names which can be used to refer to registers whose values may not be known to the programmer. These meta register names are:

`%gpreg`
  The small data address register.

`%pidreg`
  The PID base address register.

Both registers normally have the value r13, but this can change if some registers have been reserved for use by interrupt handlers or if both the small data limit and position independent data features are being used at the same time.

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### 9.33.3 Assembler Directives

The RX version of `as` has the following specific assembler directives:

`.3byte`
  Inserts a 3-byte value into the output file at the current location.

`.fetchalign`
  If the next opcode following this directive spans a fetch line boundary (8 byte boundary), the opcode is aligned to that boundary. If the next opcode does not span a fetch line, this directive has no effect. Note that one or more labels may be between this directive and the opcode; those labels are aligned as well. Any inserted bytes due to alignment will form a NOP opcode.

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### 9.33.4 Floating Point

The floating point formats generated by directives are these.

`.float`
  `Single` precision (32-bit) floating point constants.

`.double`
  If the ``-m64bit-doubles'` command line option has been specified then then `double` directive generates `double` precision (64-bit) floating point constants, otherwise it generates `single` precision (32-bit) floating point constants. To force the generation of 64-bit floating point constants used the `dc.d` directive instead.

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### 9.33.5 Syntax for the RX

> 9.33.5.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.33.5.1 Special Characters

The presence of a ``;'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``!'` character can be used to separate statements on the same line.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

## 9.34 IBM S/390 Dependent Features

The s390 version of `as` supports two architectures modes and seven chip levels. The architecture modes are the Enterprise System Architecture (ESA) and the newer z/Architecture mode. The chip levels are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12.

> 9.34.1 Options |  | Command-line Options.
> 9.34.2 Special Characters |  |
> 9.34.3 Instruction syntax |  | Assembler Instruction syntax.
> 9.34.4 Assembler Directives |  |
> 9.34.5 Floating Point |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.34.1 Options

The following table lists all available s390 specific options:

`-m31 | -m64`
  Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.

  These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 31-bit platform you must add --enable-64-bit-bfd on the call to the configure script to enable 64-bit usage and use s390x as target platform).

`-mesa | -mzarch`
  Select the architecture mode, either the Enterprise System Architecture (esa) mode or the z/Architecture mode (zarch).

  The 64-bit instructions are only available with the z/Architecture mode. The combination of ``-m64'` and ``-mesa'` results in a warning message.

`-march=CPU`
  This option specifies the target processor. The following processor names are recognized: `g5`, `g6`, `z900`, `z990`, `z9-109`, `z9-ec`, `z10` and `z196`. Assembling an instruction that is not supported on the target processor results in an error message. Do not specify `g5` or `g6` with ``-mzarch'`.

`-mregnames`
  Allow symbolic names for registers.

`-mno-regnames`
  Do not allow symbolic names for registers.

`-mwarn-areg-zero`
  Warn whenever the operand for a base or index register has been specified but evaluates to zero. This can indicate the misuse of general purpose register 0 as an address register.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.34.2 Special Characters

``#'` is the line comment character.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used instead of a newline to separate statements.

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### 9.34.3 Instruction syntax

The assembler syntax closely follows the syntax outlined in Enterprise Systems Architecture/390 Principles of Operation (SA22-7201) and the z/Architecture Principles of Operation (SA22-7832).

Each instruction has two major parts, the instruction mnemonic and the instruction operands. The instruction format varies.

> 9.34.3.1 Register naming |  | Register Naming
> 9.34.3.2 Instruction Mnemonics |  |
> 9.34.3.3 Instruction Operands |  |
> 9.34.3.4 Instruction Formats |  |
> 9.34.3.5 Instruction Aliases |  |
> 9.34.3.6 Instruction Operand Modifier |  |
> 9.34.3.7 Instruction Marker |  |
> 9.34.3.8 Literal Pool Entries |  |

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#### 9.34.3.1 Register naming

The `as` recognizes a number of predefined symbols for the various processor registers. A register specification in one of the instruction formats is an unsigned integer between 0 and 15. The specific instruction and the position of the register in the instruction format denotes the type of the register. The register symbols are prefixed with ``%'`:

    %rN  the 16 general purpose registers, 0 <= N <= 15

    %fN  the 16 floating point registers, 0 <= N <= 15

    %aN  the 16 access registers, 0 <= N <= 15

    %cN  the 16 control registers, 0 <= N <= 15

    %lit  an alias for the general purpose register %r13

    %sp  an alias for the general purpose register %r15

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#### 9.34.3.2 Instruction Mnemonics

All instructions documented in the Principles of Operation are supported with the mnemonic and order of operands as described. The instruction mnemonic identifies the instruction format (9.34.3.4 Instruction Formats) and the specific operation code for the instruction. For example, the ``lr'` mnemonic denotes the instruction format ``RR'` with the operation code ``0x18'`.

The definition of the various mnemonics follows a scheme, where the first character usually hint at the type of the instruction:

    a  add instruction, for example `al' for add logical 32-bit

    b  branch instruction, for example `bc' for branch on condition

    c  compare or convert instruction, for example `cr' for compare
    register 32-bit

    d  divide instruction, for example `dlr' devide logical register
    64-bit to 32-bit

    i  insert instruction, for example `ic' insert character

    l  load instruction, for example `ltr' load and test register

    mv  move instruction, for example `mvc' move character

    m  multiply instruction, for example `mh' multiply halfword

    n  and instruction, for example `ni' and immediate

    o  or instruction, for example `oc' or character

    sla, sll  shift left single instruction

    sra, srl  shift right single instruction

    st  store instruction, for example `stm' store multiple

    s  subtract instruction, for example `slr' subtract
    logical 32-bit

    t  test or translate instruction, of example `tm' test under mask

    x  exclusive or instruction, for example `xc' exclusive or
    character

Certain characters at the end of the mnemonic may describe a property of the instruction:

    c  the instruction uses a 8-bit character operand

    f  the instruction extends a 32-bit operand to 64 bit

    g  the operands are treated as 64-bit values

    h  the operand uses a 16-bit halfword operand

    i  the instruction uses an immediate operand

    l  the instruction uses unsigned, logical operands

    m  the instruction uses a mask or operates on multiple values

    r  if r is the last character, the instruction operates on registers

    y  the instruction uses 20-bit displacements

There are many exceptions to the scheme outlined in the above lists, in particular for the priviledged instructions. For non-priviledged instruction it works quite well, for example the instruction ``clgfr'` c: compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- to 64-bit extension, r: register operands. The instruction compares an 64-bit value in a register with the zero extended 32-bit value from a second register. For a complete list of all mnemonics see appendix B in the Principles of Operation.

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#### 9.34.3.3 Instruction Operands

Instruction operands can be grouped into three classes, operands located in registers, immediate operands, and operands in storage.

A register operand can be located in general, floating-point, access, or control register. The register is identified by a four-bit field. The field containing the register operand is called the R field.

Immediate operands are contained within the instruction and can have 8, 16 or 32 bits. The field containing the immediate operand is called the I field. Dependent on the instruction the I field is either signed or unsigned.

A storage operand consists of an address and a length. The address of a storage operands can be specified in any of these ways:

- The content of a single general R
- The sum of the content of a general register called the base register B plus the content of a displacement field D
- The sum of the contents of two general registers called the index register X and the base register B plus the content of a displacement field
- The sum of the current instruction address and a 32-bit signed immediate field multiplied by two.

The length of a storage operand can be:

- Implied by the instruction
- Specified by a bitmask
- Specified by a four-bit or eight-bit length field L
- Specified by the content of a general register

The notation for storage operand addresses formed from multiple fields is as follows:

`Dn(Bn)`
  the address for operand number n is formed from the content of general register Bn called the base register and the displacement field Dn.
`Dn(Xn,Bn)`
  the address for operand number n is formed from the content of general register Xn called the index register, general register Bn called the base register and the displacement field Dn.
`Dn(Ln,Bn)`
  the address for operand number n is formed from the content of general regiser Bn called the base register and the displacement field Dn. The length of the operand n is specified by the field Ln.

The base registers Bn and the index registers Xn of a storage operand can be skipped. If Bn and Xn are skipped, a zero will be stored to the operand field. The notation changes as follows:

    @headitem full notation
| short notation
Dn(0,Bn) | Dn(Bn)
Dn(0,0) | Dn
Dn(0) | Dn
Dn(Ln,0) | Dn(Ln)

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#### 9.34.3.4 Instruction Formats

The Principles of Operation manuals lists 26 instruction formats where some of the formats have multiple variants. For the ``.insn'` pseudo directive the assembler recognizes some of the formats. Typically, the most general variant of the instruction format is used by the ``.insn'` directive.

The following table lists the abbreviations used in the table of instruction formats:

    OpCode / OpCd  Part of the op code.

    Bx  Base register number for operand x.

    Dx  Displacement for operand x.

    DLx  Displacement lower 12 bits for operand x.

    DHx  Displacement higher 8-bits for operand x.

    Rx  Register number for operand x.

    Xx  Index register number for operand x.

    Ix  Signed immediate for operand x.

    Ux  Unsigned immediate for operand x.

An instruction is two, four, or six bytes in length and must be aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00 indicates a two byte instruction, 01 and 10 indicates a four byte instruction, and 11 indicates a six byte instruction.

The following table lists the s390 instruction formats that are available with the ``.insn'` pseudo directive:

`E format`
  @verbatim +-------------+ | OpCode | +-------------+ 0 15

`RI format: <insn> R1,I2`
  @verbatim +--------+----+----+------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------+ 0 8 12 16 31

`RIE format: <insn> R1,R3,I2`
  @verbatim +--------+----+----+------------------+--------+--------+ | OpCode | R1 | R3 | I2 |////////| OpCode | +--------+----+----+------------------+--------+--------+ 0 8 12 16 32 40 47

`RIL format: <insn> R1,I2`
  @verbatim +--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47

`RILU format: <insn> R1,U2`
  @verbatim +--------+----+----+------------------------------------+ | OpCode | R1 |OpCd| U2 | +--------+----+----+------------------------------------+ 0 8 12 16 47

`RIS format: <insn> R1,I2,M3,D4(B4)`
  @verbatim +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 47

`RR format: <insn> R1,R2`
  @verbatim +--------+----+----+ | OpCode | R1 | R2 | +--------+----+----+ 0 8 12 15

`RRE format: <insn> R1,R2`
  @verbatim +------------------+--------+----+----+ | OpCode |////////| R1 | R2 | +------------------+--------+----+----+ 0 16 24 28 31

`RRF format: <insn> R1,R2,R3,M4`
  @verbatim +------------------+----+----+----+----+ | OpCode | R3 | M4 | R1 | R2 | +------------------+----+----+----+----+ 0 16 20 24 28 31

`RRS format: <insn> R1,R2,M3,D4(B4)`
  @verbatim +--------+----+----+----+-------------+----+----+--------+ | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | +--------+----+----+----+-------------+----+----+--------+ 0 8 12 16 20 32 36 40 47

`RS format: <insn> R1,R3,D2(B2)`
  @verbatim +--------+----+----+----+-------------+ | OpCode | R1 | R3 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31

`RSE format: <insn> R1,R3,D2(B2)`
  @verbatim +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47

`RSI format: <insn> R1,R3,I2`
  @verbatim +--------+----+----+------------------------------------+ | OpCode | R1 | R3 | I2 | +--------+----+----+------------------------------------+ 0 8 12 16 47

`RSY format: <insn> R1,R3,D2(B2)`
  @verbatim +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47

`RX format: <insn> R1,D2(X2,B2)`
  @verbatim +--------+----+----+----+-------------+ | OpCode | R1 | X2 | B2 | D2 | +--------+----+----+----+-------------+ 0 8 12 16 20 31

`RXE format: <insn> R1,D2(X2,B2)`
  @verbatim +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 40 47

`RXF format: <insn> R1,R3,D2(X2,B2)`
  @verbatim +--------+----+----+----+-------------+----+---+--------+ | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | +--------+----+----+----+-------------+----+---+--------+ 0 8 12 16 20 32 36 40 47

`RXY format: <insn> R1,D2(X2,B2)`
  @verbatim +--------+----+----+----+-------------+--------+--------+ | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | +--------+----+----+----+-------------+--------+--------+ 0 8 12 16 20 32 36 40 47

`S format: <insn> D2(B2)`
  @verbatim +------------------+----+-------------+ | OpCode | B2 | D2 | +------------------+----+-------------+ 0 16 20 31

`SI format: <insn> D1(B1),I2`
  @verbatim +--------+---------+----+-------------+ | OpCode | I2 | B1 | D1 | +--------+---------+----+-------------+ 0 8 16 20 31

`SIY format: <insn> D1(B1),U2`
  @verbatim +--------+---------+----+-------------+--------+--------+ | OpCode | I2 | B1 | DL1 | DH1 | OpCode | +--------+---------+----+-------------+--------+--------+ 0 8 16 20 32 36 40 47

`SIL format: <insn> D1(B1),I2`
  @verbatim +------------------+----+-------------+-----------------+ | OpCode | B1 | D1 | I2 | +------------------+----+-------------+-----------------+ 0 16 20 32 47

`SS format: <insn> D1(R1,B1),D2(B3),R3`
  @verbatim +--------+----+----+----+-------------+----+------------+ | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47

`SSE format: <insn> D1(B1),D2(B2)`
  @verbatim +------------------+----+-------------+----+------------+ | OpCode | B1 | D1 | B2 | D2 | +------------------+----+-------------+----+------------+ 0 8 12 16 20 32 36 47

`SSF format: <insn> D1(B1),D2(B2),R3`
  @verbatim +--------+----+----+----+-------------+----+------------+ | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | +--------+----+----+----+-------------+----+------------+ 0 8 12 16 20 32 36 47

For the complete list of all instruction format variants see the Principles of Operation manuals.

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#### 9.34.3.5 Instruction Aliases

A specific bit pattern can have multiple mnemonics, for example the bit pattern ``0xa7000000'` has the mnemonics ``tmh'` and ``tmlh'`. In addition, there are a number of mnemonics recognized by `as` that are not present in the Principles of Operation. These are the short forms of the branch instructions, where the condition code mask operand is encoded in the mnemonic. This is relevant for the branch instructions, the compare and branch instructions, and the compare and trap instructions.

For the branch instructions there are 20 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format:

    @headitem instruction
| short form
bcr M1,R2 | b<m>r R2
bc M1,D2(X2,B2) | b<m> D2(X2,B2)
brc M1,I2 | j<m> I2
brcl M1,I2 | jg<m> I2

In the mnemonic for a branch instruction the condition code string <m> can be any of the following:

    o  jump on overflow / if ones

    h  jump on A high

    p  jump on plus

    nle  jump on not low or equal

    l  jump on A low

    m  jump on minus

    nhe  jump on not high or equal

    lh  jump on low or high

    ne  jump on A not equal B

    nz  jump on not zero / if not zeros

    e  jump on A equal B

    z  jump on zero / if zeroes

    nlh  jump on not low or high

    he  jump on high or equal

    nl  jump on A not low

    nm  jump on not minus / if not mixed

    le  jump on low or equal

    nh  jump on A not high

    np  jump on not plus

    no  jump on not overflow / if not ones

For the compare and branch, and compare and trap instructions there are 12 condition code strings that can be used as part of the mnemonic in place of a mask operand in the instruction format:

    @headitem instruction
| short form
crb R1,R2,M3,D4(B4) | crb<m> R1,R2,D4(B4)
cgrb R1,R2,M3,D4(B4) | cgrb<m> R1,R2,D4(B4)
crj R1,R2,M3,I4 | crj<m> R1,R2,I4
cgrj R1,R2,M3,I4 | cgrj<m> R1,R2,I4
cib R1,I2,M3,D4(B4) | cib<m> R1,I2,D4(B4)
cgib R1,I2,M3,D4(B4) | cgib<m> R1,I2,D4(B4)
cij R1,I2,M3,I4 | cij<m> R1,I2,I4
cgij R1,I2,M3,I4 | cgij<m> R1,I2,I4
crt R1,R2,M3 | crt<m> R1,R2
cgrt R1,R2,M3 | cgrt<m> R1,R2
cit R1,I2,M3 | cit<m> R1,I2
cgit R1,I2,M3 | cgit<m> R1,I2
clrb R1,R2,M3,D4(B4) | clrb<m> R1,R2,D4(B4)
clgrb R1,R2,M3,D4(B4) | clgrb<m> R1,R2,D4(B4)
clrj R1,R2,M3,I4 | clrj<m> R1,R2,I4
clgrj R1,R2,M3,I4 | clgrj<m> R1,R2,I4
clib R1,I2,M3,D4(B4) | clib<m> R1,I2,D4(B4)
clgib R1,I2,M3,D4(B4) | clgib<m> R1,I2,D4(B4)
clij R1,I2,M3,I4 | clij<m> R1,I2,I4
clgij R1,I2,M3,I4 | clgij<m> R1,I2,I4
clrt R1,R2,M3 | clrt<m> R1,R2
clgrt R1,R2,M3 | clgrt<m> R1,R2
clfit R1,I2,M3 | clfit<m> R1,I2
clgit R1,I2,M3 | clgit<m> R1,I2

In the mnemonic for a compare and branch and compare and trap instruction the condition code string <m> can be any of the following:

    h  jump on A high

    nle  jump on not low or equal

    l  jump on A low

    nhe  jump on not high or equal

    ne  jump on A not equal B

    lh  jump on low or high

    e  jump on A equal B

    nlh  jump on not low or high

    nl  jump on A not low

    he  jump on high or equal

    nh  jump on A not high

    le  jump on low or equal

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#### 9.34.3.6 Instruction Operand Modifier

If a symbol modifier is attached to a symbol in an expression for an instruction operand field, the symbol term is replaced with a reference to an object in the global offset table (GOT) or the procedure linkage table (PLT). The following expressions are allowed: ``symbol@modifier + constant'`, ``symbol@modifier + label + constant'`, and ``symbol@modifier - label + constant'`. The term ``symbol'` is the symbol that will be entered into the GOT or PLT, ``label'` is a local label, and ``constant'` is an arbitrary expression that the assembler can evaluate to a constant value.

The term ``(symbol + constant1)@modifier +/- label + constant2'` is also accepted but a warning message is printed and the term is converted to ``symbol@modifier +/- label + constant1 + constant2'`.

`@got`
`@got12`
  The @got modifier can be used for displacement fields, 16-bit immediate fields and 32-bit pc-relative immediate fields. The @got12 modifier is synonym to @got. The symbol is added to the GOT. For displacement fields and 16-bit immediate fields the symbol term is replaced with the offset from the start of the GOT to the GOT slot for the symbol. For a 32-bit pc-relative field the pc-relative offset to the GOT slot from the current instruction address is used.
`@gotent`
  The @gotent modifier can be used for 32-bit pc-relative immediate fields. The symbol is added to the GOT and the symbol term is replaced with the pc-relative offset from the current instruction to the GOT slot for the symbol.
`@gotoff`
  The @gotoff modifier can be used for 16-bit immediate fields. The symbol term is replaced with the offset from the start of the GOT to the address of the symbol.
`@gotplt`
  The @gotplt modifier can be used for displacement fields, 16-bit immediate fields, and 32-bit pc-relative immediate fields. A procedure linkage table entry is generated for the symbol and a jump slot for the symbol is added to the GOT. For displacement fields and 16-bit immediate fields the symbol term is replaced with the offset from the start of the GOT to the jump slot for the symbol. For a 32-bit pc-relative field the pc-relative offset to the jump slot from the current instruction address is used.
`@plt`
  The @plt modifier can be used for 16-bit and 32-bit pc-relative immediate fields. A procedure linkage table entry is generated for the symbol. The symbol term is replaced with the relative offset from the current instruction to the PLT entry for the symbol.
`@pltoff`
  The @pltoff modifier can be used for 16-bit immediate fields. The symbol term is replaced with the offset from the start of the PLT to the address of the symbol.
`@gotntpoff`
  The @gotntpoff modifier can be used for displacement fields. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT. The symbol term is replaced with the offset to the GOT slot from the start of the GOT.
`@indntpoff`
  The @indntpoff modifier can be used for 32-bit pc-relative immediate fields. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT. The symbol term is replaced with the pc-relative offset to the GOT slot from the current instruction address.

For more information about the thread local storage modifiers ``gotntpoff'` and ``indntpoff'` see the ELF extension documentation ``ELF Handling For Thread-Local Storage'`.

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#### 9.34.3.7 Instruction Marker

The thread local storage instruction markers are used by the linker to perform code optimization.

`:tls_load`
  The :tls_load marker is used to flag the load instruction in the initial exec TLS model that retrieves the offset from the thread pointer to a thread local storage variable from the GOT.
`:tls_gdcall`
  The :tls_gdcall marker is used to flag the branch-and-save instruction to the __tls_get_offset function in the global dynamic TLS model.
`:tls_ldcall`
  The :tls_ldcall marker is used to flag the branch-and-save instruction to the __tls_get_offset function in the local dynamic TLS model.

For more information about the thread local storage instruction marker and the linker optimizations see the ELF extension documentation ``ELF Handling For Thread-Local Storage'`.

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#### 9.34.3.8 Literal Pool Entries

A literal pool is a collection of values. To access the values a pointer to the literal pool is loaded to a register, the literal pool register. Usually, register %r13 is used as the literal pool register (9.34.3.1 Register naming). Literal pool entries are created by adding the suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an instruction operand. The expression is added to the literal pool and the operand is replaced with the offset to the literal in the literal pool.

`:lit1`
  The literal pool entry is created as an 8-bit value. An operand modifier must not be used for the original expression.
`:lit2`
  The literal pool entry is created as a 16 bit value. The operand modifier @got may be used in the original expression. The term ``x@got:lit2'` will put the got offset for the global symbol x to the literal pool as 16 bit value.
`:lit4`
  The literal pool entry is created as a 32-bit value. The operand modifier @got and @plt may be used in the original expression. The term ``x@got:lit4'` will put the got offset for the global symbol x to the literal pool as a 32-bit value. The term ``x@plt:lit4'` will put the plt offset for the global symbol x to the literal pool as a 32-bit value.
`:lit8`
  The literal pool entry is created as a 64-bit value. The operand modifier @got and @plt may be used in the original expression. The term ``x@got:lit8'` will put the got offset for the global symbol x to the literal pool as a 64-bit value. The term ``x@plt:lit8'` will put the plt offset for the global symbol x to the literal pool as a 64-bit value.

The assembler directive ``.ltorg'` is used to emit all literal pool entries to the current position.

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### 9.34.4 Assembler Directives

`as` for s390 supports all of the standard ELF assembler directives as outlined in the main part of this document. Some directives have been extended and there are some additional directives, which are only available for the s390 `as`.

`.insn`
  This directive permits the numeric representation of an instructions and makes the assembler insert the operands according to one of the instructions formats for ``.insn'` (9.34.3.4 Instruction Formats). For example, the instruction ``l %r1,24(%r15)'` could be written as ``.insn rx,0x58000000,%r1,24(%r15)'`.
`.short`
`.long`
`.quad`
  This directive places one or more 16-bit (.short), 32-bit (.long), or 64-bit (.quad) values into the current section. If an ELF or TLS modifier is used only the following expressions are allowed: ``symbol@modifier + constant'`, ``symbol@modifier + label + constant'`, and ``symbol@modifier - label + constant'`. The following modifiers are available:
  `@got`
  `@got12`
    The @got modifier can be used for .short, .long and .quad. The @got12 modifier is synonym to @got. The symbol is added to the GOT. The symbol term is replaced with offset from the start of the GOT to the GOT slot for the symbol.
  `@gotoff`
    The @gotoff modifier can be used for .short, .long and .quad. The symbol term is replaced with the offset from the start of the GOT to the address of the symbol.
  `@gotplt`
    The @gotplt modifier can be used for .long and .quad. A procedure linkage table entry is generated for the symbol and a jump slot for the symbol is added to the GOT. The symbol term is replaced with the offset from the start of the GOT to the jump slot for the symbol.
  `@plt`
    The @plt modifier can be used for .long and .quad. A procedure linkage table entry us generated for the symbol. The symbol term is replaced with the address of the PLT entry for the symbol.
  `@pltoff`
    The @pltoff modifier can be used for .short, .long and .quad. The symbol term is replaced with the offset from the start of the PLT to the address of the symbol.
  `@tlsgd`
  `@tlsldm`
    The @tlsgd and @tlsldm modifier can be used for .long and .quad. A tls_index structure for the symbol is added to the GOT. The symbol term is replaced with the offset from the start of the GOT to the tls_index structure.
  `@gotntpoff`
  `@indntpoff`
    The @gotntpoff and @indntpoff modifier can be used for .long and .quad. The symbol is added to the static TLS block and the negated offset to the symbol in the static TLS block is added to the GOT. For @gotntpoff the symbol term is replaced with the offset from the start of the GOT to the GOT slot, for @indntpoff the symbol term is replaced with the address of the GOT slot.
  `@dtpoff`
    The @dtpoff modifier can be used for .long and .quad. The symbol term is replaced with the offset of the symbol relative to the start of the TLS block it is contained in.
  `@ntpoff`
    The @ntpoff modifier can be used for .long and .quad. The symbol term is replaced with the offset of the symbol relative to the TCB pointer.

  For more information about the thread local storage modifiers see the ELF extension documentation ``ELF Handling For Thread-Local Storage'`.

`.ltorg`
  This directive causes the current contents of the literal pool to be dumped to the current location (9.34.3.8 Literal Pool Entries).

`.machine string`
  This directive allows you to change the machine for which code is generated. `string` may be any of the `-march=` selection options (without the -march=), `push`, or `pop`. `.machine push` saves the currently selected cpu, which may be restored with `.machine pop`. Be aware that the cpu string has to be put into double quotes in case it contains characters not appropriate for identifiers. So you have to write `"z9-109"` instead of just `z9-109`.

`.machinemode string`
  This directive allows to change the architecture mode for which code is being generated. `string` may be `esa`, `zarch`, `zarch_nohighgprs`, `push`, or `pop`. `.machinemode zarch_nohighgprs` can be used to prevent the `highgprs` flag from being set in the ELF header of the output file. This is useful in situations where the code is gated with a runtime check which makes sure that the code is only executed on kernels providing the `highgprs` feature. `.machinemode push` saves the currently selected mode, which may be restored with `.machinemode pop`.

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### 9.34.5 Floating Point

The assembler recognizes both the IEEE floating-point instruction and the hexadecimal floating-point instructions. The floating-point constructors ``.float'`, ``.single'`, and ``.double'` always emit the IEEE format. To assemble hexadecimal floating-point constants the ``.long'` and ``.quad'` directives must be used.

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## 9.35 SCORE Dependent Features

> 9.35.1 Options |  | Assembler options
> 9.35.2 SCORE Assembler Directives |  |
> 9.35.3 SCORE Syntax |  | Syntax

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.35.1 Options

The following table lists all available SCORE options.

`-G num`
  This option sets the largest size of an object that can be referenced implicitly with the `gp` register. The default value is 8.

`-EB`
  Assemble code for a big-endian cpu

`-EL`
  Assemble code for a little-endian cpu

`-FIXDD`
  Assemble code for fix data dependency

`-NWARN`
  Assemble code for no warning message for fix data dependency

`-SCORE5`
  Assemble code for target is SCORE5

`-SCORE5U`
  Assemble code for target is SCORE5U

`-SCORE7`
  Assemble code for target is SCORE7, this is default setting

`-SCORE3`
  Assemble code for target is SCORE3

`-march=score7`
  Assemble code for target is SCORE7, this is default setting

`-march=score3`
  Assemble code for target is SCORE3

`-USE_R1`
  Assemble code for no warning message when using temp register r1

`-KPIC`
  Generate code for PIC. This option tells the assembler to generate score position-independent macro expansions. It also tells the assembler to mark the output file as PIC.

`-O0`
  Assembler will not perform any optimizations

`-V`
  Sunplus release version

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.35.2 SCORE Assembler Directives

A number of assembler directives are available for SCORE. The following table is far from complete.

`.set nwarn`
  Let the assembler not to generate warnings if the source machine language instructions happen data dependency.

`.set fixdd`
  Let the assembler to insert bubbles (32 bit nop instruction / 16 bit nop! Instruction) if the source machine language instructions happen data dependency.

`.set nofixdd`
  Let the assembler to generate warnings if the source machine language instructions happen data dependency. (Default)

`.set r1`
  Let the assembler not to generate warnings if the source program uses r1. allow user to use r1

`set nor1`
  Let the assembler to generate warnings if the source program uses r1. (Default)

`.sdata`
  Tell the assembler to add subsequent data into the sdata section

`.rdata`
  Tell the assembler to add subsequent data into the rdata section

`.frame "frame-register", "offset", "return-pc-register"`
  Describe a stack frame. "frame-register" is the frame register, "offset" is the distance from the frame register to the virtual frame pointer, "return-pc-register" is the return program register. You must use ".ent" before ".frame" and only one ".frame" can be used per ".ent".

`.mask "bitmask", "frameoffset"`
  Indicate which of the integer registers are saved in the current function's stack frame, this is for the debugger to explain the frame chain.

`.ent "proc-name"`
  Set the beginning of the procedure "proc_name". Use this directive when you want to generate information for the debugger.

`.end proc-name`
  Set the end of a procedure. Use this directive to generate information for the debugger.

`.bss`
  Switch the destination of following statements into the bss section, which is used for data that is uninitialized anywhere.

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### 9.35.3 SCORE Syntax

> 9.35.3.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.35.3.1 Special Characters

The presence of a ``#'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.36 Renesas / SuperH SH Dependent Features

> 9.36.1 Options |  |
> 9.36.2 Syntax |  |
> 9.36.3 Floating Point |  |
> 9.36.4 SH Machine Directives |  |
> 9.36.5 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.36.1 Options

`as` has following command-line options for the Renesas (formerly Hitachi) / SuperH SH family.

`--little`
  Generate little endian code.

`--big`
  Generate big endian code.

`--relax`
  Alter jump instructions for long displacements.

`--small`
  Align sections to 4 byte boundaries, not 16.

`--dsp`
  Enable sh-dsp insns, and disable sh3e / sh4 insns.

`--renesas`
  Disable optimization with section symbol for compatibility with Renesas assembler.

`--allow-reg-prefix`
  Allow '$' as a register name prefix.

`--fdpic`
  Generate an FDPIC object file.

`--isa=sh4 | sh4a`
  Specify the sh4 or sh4a instruction set.
`--isa=dsp`
  Enable sh-dsp insns, and disable sh3e / sh4 insns.
`--isa=fp`
  Enable sh2e, sh3e, sh4, and sh4a insn sets.
`--isa=all`
  Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.

`-h-tick-hex`
  Support H'00 style hex constants in addition to 0x00 style.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.36.2 Syntax

> 9.36.2.1 Special Characters |  |
> 9.36.2.2 Register Names |  |
> 9.36.2.3 Addressing Modes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.36.2.1 Special Characters

``!'` is the line comment character.

You can use ``;'` instead of a newline to separate statements.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Since ``$'` has no special meaning, you may use it in symbol names.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.36.2.2 Register Names

You can use the predefined symbols ``r0'`, ``r1'`, ``r2'`, ``r3'`, ``r4'`, ``r5'`, ``r6'`, ``r7'`, ``r8'`, ``r9'`, ``r10'`, ``r11'`, ``r12'`, ``r13'`, ``r14'`, and ``r15'` to refer to the SH registers.

The SH also has these control registers:

`pr`
  procedure register (holds return address)

`pc`
  program counter

`mach`
`macl`
  high and low multiply accumulator registers

`sr`
  status register

`gbr`
  global base register

`vbr`
  vector base register (for interrupt vectors)

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.36.2.3 Addressing Modes

`as` understands the following addressing modes for the SH. `Rn` in the following refers to any of the numbered registers, but not the control registers.

`Rn`
  Register direct

`@Rn`
  Register indirect

`@-Rn`
  Register indirect with pre-decrement

`@Rn+`
  Register indirect with post-increment

`@(disp, Rn)`
  Register indirect with displacement

`@(R0, Rn)`
  Register indexed

`@(disp, GBR)`
  `GBR` offset

`@(R0, GBR)`
  GBR indexed

`addr`
`@(disp, PC)`
  PC relative address (for branch or for addressing memory). The `as` implementation allows you to use the simpler form addr anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.

`#imm`
  Immediate data

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.36.3 Floating Point

SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other SH groups can use `.float` directive to generate IEEE floating-point numbers.

SH2E and SH3E support single-precision floating point calculations as well as entirely PCAPI compatible emulation of double-precision floating point calculations. SH2E and SH3E instructions are a subset of the floating point calculations conforming to the IEEE754 standard.

In addition to single-precision and double-precision floating-point operation capability, the on-chip FPU of SH4 has a 128-bit graphic engine that enables 32-bit floating-point data to be processed 128 bits at a time. It also supports 4 * 4 array operations and inner product operations. Also, a superscalar architecture is employed that enables simultaneous execution of two instructions (including FPU instructions), providing performance of up to twice that of conventional architectures at the same frequency.

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### 9.36.4 SH Machine Directives

`uaword`
`ualong`
`uaquad`
  `as` will issue a warning when a misaligned `.word`, `.long`, or `.quad` directive is used. You may use `.uaword`, `.ualong`, or `.uaquad` to indicate that the value is intentionally misaligned.

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### 9.36.5 Opcodes

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Renesas) or SH-4 32-bit CPU Core Architecture (SuperH) and SuperH (SH) 64-Bit RISC Series (SuperH).

`as` implements all the standard SH opcodes. No additional pseudo-instructions are needed on this family. Note, however, that because `as` supports a simpler form of PC-relative addressing, you may simply write (for example)

    mov.l  bar,r0

where other assemblers might require an explicit displacement to `bar` from the program counter:

    mov.l  @(disp, PC)

Here is a summary of SH opcodes:

    Legend:
    Rn        a numbered register
    Rm        another numbered register
    #imm      immediate data
    disp      displacement
    disp8     8-bit displacement
    disp12    12-bit displacement

    add #imm,Rn                    lds.l @Rn+,PR
    add Rm,Rn                      mac.w @Rm+,@Rn+
    addc Rm,Rn                     mov #imm,Rn
    addv Rm,Rn                     mov Rm,Rn
    and #imm,R0                    mov.b Rm,@(R0,Rn)
    and Rm,Rn                      mov.b Rm,@-Rn
    and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
    bf disp8                       mov.b @(disp,Rm),R0
    bra disp12                     mov.b @(disp,GBR),R0
    bsr disp12                     mov.b @(R0,Rm),Rn
    bt disp8                       mov.b @Rm+,Rn
    clrmac                         mov.b @Rm,Rn
    clrt                           mov.b R0,@(disp,Rm)
    cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
    cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
    cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
    cmp/gt Rm,Rn                   mov.l Rm,@-Rn
    cmp/hi Rm,Rn                   mov.l Rm,@Rn
    cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
    cmp/pl Rn                      mov.l @(disp,GBR),R0
    cmp/pz Rn                      mov.l @(disp,PC),Rn
    cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
    div0s Rm,Rn                    mov.l @Rm+,Rn
    div0u                          mov.l @Rm,Rn
    div1 Rm,Rn                     mov.l R0,@(disp,GBR)
    exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
    exts.w Rm,Rn                   mov.w Rm,@-Rn
    extu.b Rm,Rn                   mov.w Rm,@Rn
    extu.w Rm,Rn                   mov.w @(disp,Rm),R0
    jmp @Rn                        mov.w @(disp,GBR),R0
    jsr @Rn                        mov.w @(disp,PC),Rn
    ldc Rn,GBR                     mov.w @(R0,Rm),Rn
    ldc Rn,SR                      mov.w @Rm+,Rn
    ldc Rn,VBR                     mov.w @Rm,Rn
    ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
    ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
    ldc.l @Rn+,VBR                 mova @(disp,PC),R0
    lds Rn,MACH                    movt Rn
    lds Rn,MACL                    muls Rm,Rn
    lds Rn,PR                      mulu Rm,Rn
    lds.l @Rn+,MACH                neg Rm,Rn
    lds.l @Rn+,MACL                negc Rm,Rn
    nop                            stc VBR,Rn
    not Rm,Rn                      stc.l GBR,@-Rn
    or #imm,R0                     stc.l SR,@-Rn
    or Rm,Rn                       stc.l VBR,@-Rn
    or.b #imm,@(R0,GBR)            sts MACH,Rn
    rotcl Rn                       sts MACL,Rn
    rotcr Rn                       sts PR,Rn
    rotl Rn                        sts.l MACH,@-Rn
    rotr Rn                        sts.l MACL,@-Rn
    rte                            sts.l PR,@-Rn
    rts                            sub Rm,Rn
    sett                           subc Rm,Rn
    shal Rn                        subv Rm,Rn
    shar Rn                        swap.b Rm,Rn
    shll Rn                        swap.w Rm,Rn
    shll16 Rn                      tas.b @Rn
    shll2 Rn                       trapa #imm
    shll8 Rn                       tst #imm,R0
    shlr Rn                        tst Rm,Rn
    shlr16 Rn                      tst.b #imm,@(R0,GBR)
    shlr2 Rn                       xor #imm,R0
    shlr8 Rn                       xor Rm,Rn
    sleep                          xor.b #imm,@(R0,GBR)
    stc GBR,Rn                     xtrct Rm,Rn
    stc SR,Rn

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## 9.37 SuperH SH64 Dependent Features

> 9.37.1 Options |  |
> 9.37.2 Syntax |  |
> 9.37.3 SH64 Machine Directives |  |
> 9.37.4 Opcodes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.37.1 Options

`-isa=sh4 | sh4a`
  Specify the sh4 or sh4a instruction set.
`-isa=dsp`
  Enable sh-dsp insns, and disable sh3e / sh4 insns.
`-isa=fp`
  Enable sh2e, sh3e, sh4, and sh4a insn sets.
`-isa=all`
  Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
`-isa=shmedia | -isa=shcompact`
  Specify the default instruction set. `SHmedia` specifies the 32-bit opcodes, and `SHcompact` specifies the 16-bit opcodes compatible with previous SH families. The default depends on the ABI selected; the default for the 64-bit ABI is SHmedia, and the default for the 32-bit ABI is SHcompact. If neither the ABI nor the ISA is specified, the default is 32-bit SHcompact.

  Note that the `.mode` pseudo-op is not permitted if the ISA is not specified on the command line.

`-abi=32 | -abi=64`
  Specify the default ABI. If the ISA is specified and the ABI is not, the default ABI depends on the ISA, with SHmedia defaulting to 64-bit and SHcompact defaulting to 32-bit.

  Note that the `.abi` pseudo-op is not permitted if the ABI is not specified on the command line. When the ABI is specified on the command line, any `.abi` pseudo-ops in the source must match it.

`-shcompact-const-crange`
  Emit code-range descriptors for constants in SHcompact code sections.

`-no-mix`
  Disallow SHmedia code in the same section as constants and SHcompact code.

`-no-expand`
  Do not expand MOVI, PT, PTA or PTB instructions.

`-expand-pt32`
  With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.

`-h-tick-hex`
  Support H'00 style hex constants in addition to 0x00 style.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.37.2 Syntax

> 9.37.2.1 Special Characters |  |
> 9.37.2.2 Register Names |  |
> 9.37.2.3 Addressing Modes |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.37.2.1 Special Characters

``!'` is the line comment character.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

You can use ``;'` instead of a newline to separate statements.

Since ``$'` has no special meaning, you may use it in symbol names.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.37.2.2 Register Names

You can use the predefined symbols ``r0'` through ``r63'` to refer to the SH64 general registers, ``cr0'` through `cr63` for control registers, ``tr0'` through ``tr7'` for target address registers, ``fr0'` through ``fr63'` for single-precision floating point registers, ``dr0'` through ``dr62'` (even numbered registers only) for double-precision floating point registers, ``fv0'` through ``fv60'` (multiples of four only) for single-precision floating point vectors, ``fp0'` through ``fp62'` (even numbered registers only) for single-precision floating point pairs, ``mtrx0'` through ``mtrx48'` (multiples of 16 only) for 4x4 matrices of single-precision floating point registers, ``pc'` for the program counter, and ``fpscr'` for the floating point status and control register.

You can also refer to the control registers by the mnemonics ``sr'`, ``ssr'`, ``pssr'`, ``intevt'`, ``expevt'`, ``pexpevt'`, ``tra'`, ``spc'`, ``pspc'`, ``resvec'`, ``vbr'`, ``tea'`, ``dcr'`, ``kcr0'`, ``kcr1'`, ``ctc'`, and ``usr'`.

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.37.2.3 Addressing Modes

SH64 operands consist of either a register or immediate value. The immediate value can be a constant or label reference (or portion of a label reference), as in this example:

    	movi	4,r2
    	pt	function, tr4
    	movi	(function >> 16) & 65535,r0
    	shori	function & 65535, r0
    	ld.l	r0,4,r0

Instruction label references can reference labels in either SHmedia or SHcompact. To differentiate between the two, labels in SHmedia sections will always have the least significant bit set (i.e. they will be odd), which SHcompact labels will have the least significant bit reset (i.e. they will be even). If you need to reference the actual address of a label, you can use the `datalabel` modifier, as in this example:

    	.long	function
    	.long	datalabel function

In that example, the first longword may or may not have the least significant bit set depending on whether the label is an SHmedia label or an SHcompact label. The second longword will be the actual address of the label, regardless of what type of label it is.

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### 9.37.3 SH64 Machine Directives

In addition to the SH directives, the SH64 provides the following directives:

`.mode [shmedia|shcompact]`
`.isa [shmedia|shcompact]`
  Specify the ISA for the following instructions (the two directives are equivalent). Note that programs such as `objdump` rely on symbolic labels to determine when such mode switches occur (by checking the least significant bit of the label's address), so such mode/isa changes should always be followed by a label (in practice, this is true anyway). Note that you cannot use these directives if you didn't specify an ISA on the command line.

`.abi [32|64]`
  Specify the ABI for the following instructions. Note that you cannot use this directive unless you specified an ABI on the command line, and the ABIs specified must match.

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### 9.37.4 Opcodes

For detailed information on the SH64 machine instruction set, see SuperH 64 bit RISC Series Architecture Manual (SuperH, Inc.).

`as` implements all the standard SH64 opcodes. In addition, the following pseudo-opcodes may be expanded into one or more alternate opcodes:

`movi`
  If the value doesn't fit into a standard `movi` opcode, `as` will replace the `movi` with a sequence of `movi` and `shori` opcodes.

`pt`
  This expands to a sequence of `movi` and `shori` opcode, followed by a `ptrel` opcode, or to a `pta` or `ptb` opcode, depending on the label referenced.

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## 9.38 SPARC Dependent Features

> 9.38.1 Options |  |
> 9.38.2 Enforcing aligned data |  | Option to enforce aligned data
> 9.38.3 Sparc Syntax |  | Syntax
> 9.38.4 Floating Point |  |
> 9.38.5 Sparc Machine Directives |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

### 9.38.1 Options

The SPARC chip family includes several successive versions, using the same core instruction set, but including a few additional instructions at each version. There are exceptions to this however. For details on what instructions each variant supports, please see the chip's architecture reference manual.

By default, `as` assumes the core instruction set (SPARC v6), but "bumps" the architecture level as needed: it switches to successively higher architectures as it encounters instructions that only exist in the higher levels.

If not configured for SPARC v9 (`sparc64-*-*`) GAS will not bump past sparclite by default, an option must be passed to enable the v9 instructions.

GAS treats sparclite as being compatible with v8, unless an architecture is explicitly requested. SPARC v9 is always incompatible with sparclite.

`-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite`
`-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv`
`-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v`
`-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima`
`-Asparcvis3 | -Asparcvis3r`
  Use one of the ``-A'` options to select one of the SPARC architectures explicitly. If you select an architecture explicitly, `as` reports a fatal error if it encounters an instruction or feature requiring an incompatible or higher level.

  ``-Av8plus'`, ``-Av8plusa'`, ``-Av8plusb'`, ``-Av8plusc'`, ``-Av8plusd'`, and ``-Av8plusv'` select a 32 bit environment.

  ``-Av9'`, ``-Av9a'`, ``-Av9b'`, ``-Av9c'`, ``-Av9d'`, and ``-Av9v'` select a 64 bit environment and are not available unless GAS is explicitly configured with 64 bit environment support.

  ``-Av8plusa'` and ``-Av9a'` enable the SPARC V9 instruction set with UltraSPARC VIS 1.0 extensions.

  ``-Av8plusb'` and ``-Av9b'` enable the UltraSPARC VIS 2.0 instructions, as well as the instructions enabled by ``-Av8plusa'` and ``-Av9a'`.

  ``-Av8plusc'` and ``-Av9c'` enable the UltraSPARC Niagara instructions, as well as the instructions enabled by ``-Av8plusb'` and ``-Av9b'`.

  ``-Av8plusd'` and ``-Av9d'` enable the floating point fused multiply-add, VIS 3.0, and HPC extension instructions, as well as the instructions enabled by ``-Av8plusc'` and ``-Av9c'`.

  ``-Av8plusv'` and ``-Av9v'` enable the 'random', transactional memory, floating point unfused multiply-add, integer multiply-add, and cache sparing store instructions, as well as the instructions enabled by ``-Av8plusd'` and ``-Av9d'`.

  ``-Asparc'` specifies a v9 environment. It is equivalent to ``-Av9'` if the word size is 64-bit, and ``-Av8plus'` otherwise.

  ``-Asparcvis'` specifies a v9a environment. It is equivalent to ``-Av9a'` if the word size is 64-bit, and ``-Av8plusa'` otherwise.

  ``-Asparcvis2'` specifies a v9b environment. It is equivalent to ``-Av9b'` if the word size is 64-bit, and ``-Av8plusb'` otherwise.

  ``-Asparcfmaf'` specifies a v9b environment with the floating point fused multiply-add instructions enabled.

  ``-Asparcima'` specifies a v9b environment with the integer multiply-add instructions enabled.

  ``-Asparcvis3'` specifies a v9b environment with the VIS 3.0, HPC , and floating point fused multiply-add instructions enabled.

  ``-Asparcvis3r'` specifies a v9b environment with the VIS 3.0, HPC, transactional memory, random, and floating point unfused multiply-add instructions enabled.

`-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc`
`-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a`
`-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v`
`-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2`
`-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3`
`-xarch=sparcvis3r`
  For compatibility with the SunOS v9 assembler. These options are equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r, respectively.

`-bump`
  Warn whenever it is necessary to switch to another level. If an architecture level is explicitly requested, GAS will not issue warnings until that level is reached, and will then bump the level as required (except between incompatible levels).

`-32 | -64`
  Select the word size, either 32 bits or 64 bits. These options are only available with the ELF object file format, and require that the necessary BFD support has been included.

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### 9.38.2 Enforcing aligned data

SPARC GAS normally permits data to be misaligned. For example, it permits the `.long` pseudo-op to be used on a byte boundary. However, the native SunOS assemblers issue an error when they see misaligned data.

You can use the `--enforce-aligned-data` option to make SPARC GAS also issue an error about misaligned data, just as the SunOS assemblers do.

The `--enforce-aligned-data` option is not the default because gcc issues misaligned data pseudo-ops when it initializes certain packed data structures (structures defined using the `packed` attribute). You may have to assemble with GAS in order to initialize packed data structures in your own code.

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### 9.38.3 Sparc Syntax

The assembler syntax closely follows The Sparc Architecture Manual, versions 8 and 9, as well as most extensions defined by Sun for their UltraSPARC and Niagara line of processors.

> 9.38.3.1 Special Characters |  |
> 9.38.3.2 Register Names |  |
> 9.38.3.3 Constants |  | Constant Names
> 9.38.3.4 Relocations |  |
> 9.38.3.5 Size Translations |  |

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#### 9.38.3.1 Special Characters

A ``!'` character appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

``;'` can be used instead of a newline to separate statements.

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#### 9.38.3.2 Register Names

The Sparc integer register file is broken down into global, outgoing, local, and incoming.

- The 8 global registers are referred to as ``%gn'`.

- The 8 outgoing registers are referred to as ``%on'`.

- The 8 local registers are referred to as ``%ln'`.

- The 8 incoming registers are referred to as ``%in'`.

- The frame pointer register ``%i6'` can be referenced using the alias ``%fp'`.

- The stack pointer register ``%o6'` can be referenced using the alias ``%sp'`.

Floating point registers are simply referred to as ``%fn'`. When assembling for pre-V9, only 32 floating point registers are available. For V9 and later there are 64, but there are restrictions when referencing the upper 32 registers. They can only be accessed as double or quad, and thus only even or quad numbered accesses are allowed. For example, ``%f34'` is a legal floating point register, but ``%f35'` is not.

Certain V9 instructions allow access to ancillary state registers. Most simply they can be referred to as ``%asrn'` where n can be from 16 to 31. However, there are some aliases defined to reference ASR registers defined for various UltraSPARC processors:

- The tick compare register is referred to as ``%tick_cmpr'`.

- The system tick register is referred to as ``%stick'`. An alias, ``%sys_tick'`, exists but is deprecated and should not be used by new software.

- The system tick compare register is referred to as ``%stick_cmpr'`. An alias, ``%sys_tick_cmpr'`, exists but is deprecated and should not be used by new software.

- The software interrupt register is referred to as ``%softint'`.

- The set software interrupt register is referred to as ``%set_softint'`. The mnemonic ``%softint_set'` is provided as an alias.

- The clear software interrupt register is referred to as ``%clear_softint'`. The mnemonic ``%softint_clear'` is provided as an alias.

- The performance instrumentation counters register is referred to as ``%pic'`.

- The performance control register is referred to as ``%pcr'`.

- The graphics status register is referred to as ``%gsr'`.

- The V9 dispatch control register is referred to as ``%dcr'`.

Various V9 branch and conditional move instructions allow specification of which set of integer condition codes to test. These are referred to as ``%xcc'` and ``%icc'`.

In V9, there are 4 sets of floating point condition codes which are referred to as ``%fccn'`.

Several special privileged and non-privileged registers exist:

- The V9 address space identifier register is referred to as ``%asi'`.

- The V9 restorable windows register is referred to as ``%canrestore'`.

- The V9 savable windows register is referred to as ``%cansave'`.

- The V9 clean windows register is referred to as ``%cleanwin'`.

- The V9 current window pointer register is referred to as ``%cwp'`.

- The floating-point queue register is referred to as ``%fq'`.

- The V8 co-processor queue register is referred to as ``%cq'`.

- The floating point status register is referred to as ``%fsr'`.

- The other windows register is referred to as ``%otherwin'`.

- The V9 program counter register is referred to as ``%pc'`.

- The V9 next program counter register is referred to as ``%npc'`.

- The V9 processor interrupt level register is referred to as ``%pil'`.

- The V9 processor state register is referred to as ``%pstate'`.

- The trap base address register is referred to as ``%tba'`.

- The V9 tick register is referred to as ``%tick'`.

- The V9 trap level is referred to as ``%tl'`.

- The V9 trap program counter is referred to as ``%tpc'`.

- The V9 trap next program counter is referred to as ``%tnpc'`.

- The V9 trap state is referred to as ``%tstate'`.

- The V9 trap type is referred to as ``%tt'`.

- The V9 condition codes is referred to as ``%ccr'`.

- The V9 floating-point registers state is referred to as ``%fprs'`.

- The V9 version register is referred to as ``%ver'`.

- The V9 window state register is referred to as ``%wstate'`.

- The Y register is referred to as ``%y'`.

- The V8 window invalid mask register is referred to as ``%wim'`.

- The V8 processor state register is referred to as ``%psr'`.

- The V9 global register level register is referred to as ``%gl'`.

Several special register names exist for hypervisor mode code:

- The hyperprivileged processor state register is referred to as ``%hpstate'`.

- The hyperprivileged trap state register is referred to as ``%htstate'`.

- The hyperprivileged interrupt pending register is referred to as ``%hintp'`.

- The hyperprivileged trap base address register is referred to as ``%htba'`.

- The hyperprivileged implementation version register is referred to as ``%hver'`.

- The hyperprivileged system tick compare register is referred to as ``%hstick_cmpr'`. Note that there is no ``%hstick'` register, the normal ``%stick'` is used.

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#### 9.38.3.3 Constants

Several Sparc instructions take an immediate operand field for which mnemonic names exist. Two such examples are ``membar'` and ``prefetch'`. Another example are the set of V9 memory access instruction that allow specification of an address space identifier.

The ``membar'` instruction specifies a memory barrier that is the defined by the operand which is a bitmask. The supported mask mnemonics are:

- ``#Sync'` requests that all operations (including nonmemory reference operations) appearing prior to the `membar` must have been performed and the effects of any exceptions become visible before any instructions after the `membar` may be initiated. This corresponds to `membar` cmask field bit 2.

- ``#MemIssue'` requests that all memory reference operations appearing prior to the `membar` must have been performed before any memory operation after the `membar` may be initiated. This corresponds to `membar` cmask field bit 1.

- ``#Lookaside'` requests that a store appearing prior to the `membar` must complete before any load following the `membar` referencing the same address can be initiated. This corresponds to `membar` cmask field bit 0.

- ``#StoreStore'` defines that the effects of all stores appearing prior to the `membar` instruction must be visible to all processors before the effect of any stores following the `membar`. Equivalent to the deprecated `stbar` instruction. This corresponds to `membar` mmask field bit 3.

- ``#LoadStore'` defines all loads appearing prior to the `membar` instruction must have been performed before the effect of any stores following the `membar` is visible to any other processor. This corresponds to `membar` mmask field bit 2.

- ``#StoreLoad'` defines that the effects of all stores appearing prior to the `membar` instruction must be visible to all processors before loads following the `membar` may be performed. This corresponds to `membar` mmask field bit 1.

- ``#LoadLoad'` defines that all loads appearing prior to the `membar` instruction must have been performed before any loads following the `membar` may be performed. This corresponds to `membar` mmask field bit 0.

These values can be ored together, for example:

    membar #Sync
    membar #StoreLoad | #LoadLoad
    membar #StoreLoad | #StoreStore

The `prefetch` and `prefetcha` instructions take a prefetch function code. The following prefetch function code constant mnemonics are available:

- ``#n_reads'` requests a prefetch for several reads, and corresponds to a prefetch function code of 0.

  ``#one_read'` requests a prefetch for one read, and corresponds to a prefetch function code of 1.

  ``#n_writes'` requests a prefetch for several writes (and possibly reads), and corresponds to a prefetch function code of 2.

  ``#one_write'` requests a prefetch for one write, and corresponds to a prefetch function code of 3.

  ``#page'` requests a prefetch page, and corresponds to a prefetch function code of 4.

  ``#invalidate'` requests a prefetch invalidate, and corresponds to a prefetch function code of 16.

  ``#unified'` requests a prefetch to the nearest unified cache, and corresponds to a prefetch function code of 17.

  ``#n_reads_strong'` requests a strong prefetch for several reads, and corresponds to a prefetch function code of 20.

  ``#one_read_strong'` requests a strong prefetch for one read, and corresponds to a prefetch function code of 21.

  ``#n_writes_strong'` requests a strong prefetch for several writes, and corresponds to a prefetch function code of 22.

  ``#one_write_strong'` requests a strong prefetch for one write, and corresponds to a prefetch function code of 23.

  Onle one prefetch code may be specified. Here are some examples:

      prefetch  [%l0 + %l2], #one_read
      prefetch  [%g2 + 8], #n_writes
      prefetcha [%g1] 0x8, #unified
      prefetcha [%o0 + 0x10] %asi, #n_reads

  The actual behavior of a given prefetch function code is processor specific. If a processor does not implement a given prefetch function code, it will treat the prefetch instruction as a nop.

  For instructions that accept an immediate address space identifier, `as` provides many mnemonics corresponding to V9 defined as well as UltraSPARC and Niagara extended values. For example, ``#ASI_P'` and ``#ASI_BLK_INIT_QUAD_LDD_AIUS'`. See the V9 and processor specific manuals for details.

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#### 9.38.3.4 Relocations

ELF relocations are available as defined in the 32-bit and 64-bit Sparc ELF specifications.

`R_SPARC_HI22` is obtained using ``%hi'` and `R_SPARC_LO10` is obtained using ``%lo'`. Likewise `R_SPARC_HIX22` is obtained from ``%hix'` and `R_SPARC_LOX10` is obtained using ``%lox'`. For example:

    sethi %hi(symbol), %g1
    or    %g1, %lo(symbol), %g1

    sethi %hix(symbol), %g1
    xor   %g1, %lox(symbol), %g1

These "high" mnemonics extract bits 31:10 of their operand, and the "low" mnemonics extract bits 9:0 of their operand.

V9 code model relocations can be requested as follows:

- `R_SPARC_HH22` is requested using ``%hh'`. It can also be generated using ``%uhi'`.
- `R_SPARC_HM10` is requested using ``%hm'`. It can also be generated using ``%ulo'`.
- `R_SPARC_LM22` is requested using ``%lm'`.

- `R_SPARC_H44` is requested using ``%h44'`.
- `R_SPARC_M44` is requested using ``%m44'`.
- `R_SPARC_L44` is requested using ``%l44'` or ``%l34'`.
- `R_SPARC_H34` is requested using ``%h34'`.

The ``%l34'` generates a `R_SPARC_L44` relocation because it calculates the necessary value, and therefore no explicit `R_SPARC_L34` relocation needed to be created for this purpose.

The ``%h34'` and ``%l34'` relocations are used for the abs34 code model. Here is an example abs34 address generation sequence:

    sethi %h34(symbol), %g1
    sllx  %g1, 2, %g1
    or    %g1, %l34(symbol), %g1

The PC relative relocation `R_SPARC_PC22` can be obtained by enclosing an operand inside of ``%pc22'`. Likewise, the `R_SPARC_PC10` relocation can be obtained using ``%pc10'`. These are mostly used when assembling PIC code. For example, the standard PIC sequence on Sparc to get the base of the global offset table, PC relative, into a register, can be performed as:

    sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
    add   %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7

Several relocations exist to allow the link editor to potentially optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22` relocation can obtained by enclosing an operand inside of ``%gdop_hix22'`. The `R_SPARC_GOTDATA_OP_LOX10` relocation can obtained by enclosing an operand inside of ``%gdop_lox10'`. Likewise, `R_SPARC_GOTDATA_OP` can be obtained by enclosing an operand inside of ``%gdop'`. For example, assuming the GOT base is in register `%l7`:

    sethi %gdop_hix22(symbol), %l1
    xor   %l1, %gdop_lox10(symbol), %l1
    ld    [%l7 + %l1], %l2, %gdop(symbol)

There are many relocations that can be requested for access to thread local storage variables. All of the Sparc TLS mnemonics are supported:

- `R_SPARC_TLS_GD_HI22` is requested using ``%tgd_hi22'`.
- `R_SPARC_TLS_GD_LO10` is requested using ``%tgd_lo10'`.
- `R_SPARC_TLS_GD_ADD` is requested using ``%tgd_add'`.
- `R_SPARC_TLS_GD_CALL` is requested using ``%tgd_call'`.

- `R_SPARC_TLS_LDM_HI22` is requested using ``%tldm_hi22'`.
- `R_SPARC_TLS_LDM_LO10` is requested using ``%tldm_lo10'`.
- `R_SPARC_TLS_LDM_ADD` is requested using ``%tldm_add'`.
- `R_SPARC_TLS_LDM_CALL` is requested using ``%tldm_call'`.

- `R_SPARC_TLS_LDO_HIX22` is requested using ``%tldo_hix22'`.
- `R_SPARC_TLS_LDO_LOX10` is requested using ``%tldo_lox10'`.
- `R_SPARC_TLS_LDO_ADD` is requested using ``%tldo_add'`.

- `R_SPARC_TLS_IE_HI22` is requested using ``%tie_hi22'`.
- `R_SPARC_TLS_IE_LO10` is requested using ``%tie_lo10'`.
- `R_SPARC_TLS_IE_LD` is requested using ``%tie_ld'`.
- `R_SPARC_TLS_IE_LDX` is requested using ``%tie_ldx'`.
- `R_SPARC_TLS_IE_ADD` is requested using ``%tie_add'`.

- `R_SPARC_TLS_LE_HIX22` is requested using ``%tle_hix22'`.
- `R_SPARC_TLS_LE_LOX10` is requested using ``%tle_lox10'`.

Here are some example TLS model sequences.

First, General Dynamic:

    sethi  %tgd_hi22(symbol), %l1
    add    %l1, %tgd_lo10(symbol), %l1
    add    %l7, %l1, %o0, %tgd_add(symbol)
    call   __tls_get_addr, %tgd_call(symbol)
    nop

Local Dynamic:

    sethi  %tldm_hi22(symbol), %l1
    add    %l1, %tldm_lo10(symbol), %l1
    add    %l7, %l1, %o0, %tldm_add(symbol)
    call   __tls_get_addr, %tldm_call(symbol)
    nop

    sethi  %tldo_hix22(symbol), %l1
    xor    %l1, %tldo_lox10(symbol), %l1
    add    %o0, %l1, %l1, %tldo_add(symbol)

Initial Exec:

    sethi  %tie_hi22(symbol), %l1
    add    %l1, %tie_lo10(symbol), %l1
    ld     [%l7 + %l1], %o0, %tie_ld(symbol)
    add    %g7, %o0, %o0, %tie_add(symbol)

    sethi  %tie_hi22(symbol), %l1
    add    %l1, %tie_lo10(symbol), %l1
    ldx    [%l7 + %l1], %o0, %tie_ldx(symbol)
    add    %g7, %o0, %o0, %tie_add(symbol)

And finally, Local Exec:

    sethi  %tle_hix22(symbol), %l1
    add    %l1, %tle_lox10(symbol), %l1
    add    %g7, %l1, %l1

When assembling for 64-bit, and a secondary constant addend is specified in an address expression that would normally generate an `R_SPARC_LO10` relocation, the assembler will emit an `R_SPARC_OLO10` instead.

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#### 9.38.3.5 Size Translations

Often it is desirable to write code in an operand size agnostic manner. `as` provides support for this via operand size opcode translations. Translations are supported for loads, stores, shifts, compare-and-swap atomics, and the ``clr'` synthetic instruction.

If generating 32-bit code, `as` will generate the 32-bit opcode. Whereas if 64-bit code is being generated, the 64-bit opcode will be emitted. For example `ldn` will be transformed into `ld` for 32-bit code and `ldx` for 64-bit code.

Here is an example meant to demonstrate all the supported opcode translations:

    ldn   [%o0], %o1
    ldna  [%o0] %asi, %o2
    stn   %o1, [%o0]
    stna  %o2, [%o0] %asi
    slln  %o3, 3, %o3
    srln  %o4, 8, %o4
    sran  %o5, 12, %o5
    casn  [%o0], %o1, %o2
    casna [%o0] %asi, %o1, %o2
    clrn  %g1

In 32-bit mode `as` will emit:

    ld   [%o0], %o1
    lda  [%o0] %asi, %o2
    st   %o1, [%o0]
    sta  %o2, [%o0] %asi
    sll  %o3, 3, %o3
    srl  %o4, 8, %o4
    sra  %o5, 12, %o5
    cas  [%o0], %o1, %o2
    casa [%o0] %asi, %o1, %o2
    clr  %g1

And in 64-bit mode `as` will emit:

    ldx   [%o0], %o1
    ldxa  [%o0] %asi, %o2
    stx   %o1, [%o0]
    stxa  %o2, [%o0] %asi
    sllx  %o3, 3, %o3
    srlx  %o4, 8, %o4
    srax  %o5, 12, %o5
    casx  [%o0], %o1, %o2
    casxa [%o0] %asi, %o1, %o2
    clrx  %g1

Finally, the ``.nword'` translating directive is supported as well. It is documented in the section on Sparc machine directives.

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### 9.38.4 Floating Point

The Sparc uses IEEE floating-point numbers.

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### 9.38.5 Sparc Machine Directives

The Sparc version of `as` supports the following additional machine directives:

`.align`
  This must be followed by the desired alignment in bytes.

`.common`
  This must be followed by a symbol name, a positive number, and `"bss"`. This behaves somewhat like `.comm`, but the syntax is different.

`.half`
  This is functionally identical to `.short`.

`.nword`
  On the Sparc, the `.nword` directive produces native word sized value, ie. if assembling with -32 it is equivalent to `.word`, if assembling with -64 it is equivalent to `.xword`.

`.proc`
  This directive is ignored. Any text following it on the same line is also ignored.

`.register`
  This directive declares use of a global application or system register. It must be followed by a register name %g2, %g3, %g6 or %g7, comma and the symbol name for that register. If symbol name is `#scratch`, it is a scratch register, if it is `#ignore`, it just suppresses any errors about using undeclared global register, but does not emit any information about it into the object file. This can be useful e.g. if you save the register before use and restore it after.

`.reserve`
  This must be followed by a symbol name, a positive number, and `"bss"`. This behaves somewhat like `.lcomm`, but the syntax is different.

`.seg`
  This must be followed by `"text"`, `"data"`, or `"data1"`. It behaves like `.text`, `.data`, or `.data 1`.

`.skip`
  This is functionally identical to the `.space` directive.

`.word`
  On the Sparc, the `.word` directive produces 32 bit values, instead of the 16 bit values it produces on many other machines.

`.xword`
  On the Sparc V9 processor, the `.xword` directive produces 64 bit values.

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## 9.39 TIC54X Dependent Features

> 9.39.1 Options |  | Command-line Options
> 9.39.2 Blocking |  |
> 9.39.3 Environment Settings |  |
> 9.39.4 Constants Syntax |  |
> 9.39.5 String Substitution |  |
> 9.39.6 Local Labels |  | Local Label Syntax
> 9.39.7 Math Builtins |  | Builtin Assembler Math Functions
> 9.39.8 Extended Addressing |  | Extended Addressing Support
> 9.39.9 Directives |  |
> 9.39.10 Macros |  | Macro Features
> 9.39.11 Memory-mapped Registers |  |
> 9.39.12 TIC54X Syntax |  | Syntax

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### 9.39.1 Options

The TMS320C54X version of `as` has a few machine-dependent options.

You can use the ``-mfar-mode'` option to enable extended addressing mode. All addresses will be assumed to be > 16 bits, and the appropriate relocation types will be used. This option is equivalent to using the ``.far_mode'` directive in the assembly code. If you do not use the ``-mfar-mode'` option, all references will be assumed to be 16 bits. This option may be abbreviated to ``-mf'`.

You can use the ``-mcpu'` option to specify a particular CPU. This option is equivalent to using the ``.version'` directive in the assembly code. For recognized CPU codes, see See section `.version`. The default CPU version is ``542'`.

You can use the ``-merrors-to-file'` option to redirect error output to a file (this provided for those deficient environments which don't provide adequate output redirection). This option may be abbreviated to ``-me'`.

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### 9.39.2 Blocking

A blocked section or memory block is guaranteed not to cross the blocking boundary (usually a page, or 128 words) if it is smaller than the blocking size, or to start on a page boundary if it is larger than the blocking size.

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### 9.39.3 Environment Settings

``C54XDSP_DIR'` and ``A_DIR'` are semicolon-separated paths which are added to the list of directories normally searched for source and include files. ``C54XDSP_DIR'` will override ``A_DIR'`.

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### 9.39.4 Constants Syntax

The TIC54X version of `as` allows the following additional constant formats, using a suffix to indicate the radix:

    Binary                  000000B, 011000b
    Octal                   10Q, 224q
    Hexadecimal             45h, 0FH

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### 9.39.5 String Substitution

A subset of allowable symbols (which we'll call subsyms) may be assigned arbitrary string values. This is roughly equivalent to C preprocessor #define macros. When `as` encounters one of these symbols, the symbol is replaced in the input stream by its string value. Subsym names must begin with a letter.

Subsyms may be defined using the `.asg` and `.eval` directives (See section `.asg`, See section `.eval`.

Expansion is recursive until a previously encountered symbol is seen, at which point substitution stops.

In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1 is replaced with x. At this point, x has already been encountered and the substitution stops.

     .asg   "x",SYM1
     .asg   "SYM1",SYM2
     .asg   "SYM2",x
     add    x,a             ; final code assembled is "add  x, a"

Macro parameters are converted to subsyms; a side effect of this is the normal `as` '\ARG' dereferencing syntax is unnecessary. Subsyms defined within a macro will have global scope, unless the `.var` directive is used to identify the subsym as a local macro variable see section `.var`.

Substitution may be forced in situations where replacement might be ambiguous by placing colons on either side of the subsym. The following code:

     .eval  "10",x
    LAB:X:  add     #x, a

When assembled becomes:

    LAB10  add     #10, a

Smaller parts of the string assigned to a subsym may be accessed with the following syntax:

``:symbol(char_index):``
  Evaluates to a single-character string, the character at char_index.
``:symbol(start,length):``
  Evaluates to a substring of symbol beginning at start with length length.

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### 9.39.6 Local Labels

Local labels may be defined in two ways:

- $N, where N is a decimal number between 0 and 9
- LABEL?, where LABEL is any legal symbol name.

Local labels thus defined may be redefined or automatically generated. The scope of a local label is based on when it may be undefined or reset. This happens when one of the following situations is encountered:

- .newblock directive see section `.newblock`
- The current section is changed (.sect, .text, or .data)
- Entering or leaving an included file
- The macro scope where the label was defined is exited

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### 9.39.7 Math Builtins

The following built-in functions may be used to generate a floating-point value. All return a floating-point value except ``$cvi'`, ``$int'`, and ``$sgn'`, which return an integer value.

``$acos(expr)``
  Returns the floating point arccosine of expr.

``$asin(expr)``
  Returns the floating point arcsine of expr.

``$atan(expr)``
  Returns the floating point arctangent of expr.

``$atan2(expr1,expr2)``
  Returns the floating point arctangent of expr1 / expr2.

``$ceil(expr)``
  Returns the smallest integer not less than expr as floating point.

``$cosh(expr)``
  Returns the floating point hyperbolic cosine of expr.

``$cos(expr)``
  Returns the floating point cosine of expr.

``$cvf(expr)``
  Returns the integer value expr converted to floating-point.

``$cvi(expr)``
  Returns the floating point value expr converted to integer.

``$exp(expr)``
  Returns the floating point value e ^ expr.

``$fabs(expr)``
  Returns the floating point absolute value of expr.

``$floor(expr)``
  Returns the largest integer that is not greater than expr as floating point.

``$fmod(expr1,expr2)``
  Returns the floating point remainder of expr1 / expr2.

``$int(expr)``
  Returns 1 if expr evaluates to an integer, zero otherwise.

``$ldexp(expr1,expr2)``
  Returns the floating point value expr1 * 2 ^ expr2.

``$log10(expr)``
  Returns the base 10 logarithm of expr.

``$log(expr)``
  Returns the natural logarithm of expr.

``$max(expr1,expr2)``
  Returns the floating point maximum of expr1 and expr2.

``$min(expr1,expr2)``
  Returns the floating point minimum of expr1 and expr2.

``$pow(expr1,expr2)``
  Returns the floating point value expr1 ^ expr2.

``$round(expr)``
  Returns the nearest integer to expr as a floating point number.

``$sgn(expr)``
  Returns -1, 0, or 1 based on the sign of expr.

``$sin(expr)``
  Returns the floating point sine of expr.

``$sinh(expr)``
  Returns the floating point hyperbolic sine of expr.

``$sqrt(expr)``
  Returns the floating point square root of expr.

``$tan(expr)``
  Returns the floating point tangent of expr.

``$tanh(expr)``
  Returns the floating point hyperbolic tangent of expr.

``$trunc(expr)``
  Returns the integer value of expr truncated towards zero as floating point.

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### 9.39.8 Extended Addressing

The `LDX` pseudo-op is provided for loading the extended addressing bits of a label or address. For example, if an address `_label` resides in extended program memory, the value of `_label` may be loaded as follows:

     ldx     #_label,16,a    ; loads extended bits of _label
     or      #_label,a       ; loads lower 16 bits of _label
     bacc    a               ; full address is in accumulator A

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### 9.39.9 Directives

`.align [size]`
`.even`
  Align the section program counter on the next boundary, based on size. size may be any power of 2. `.even` is equivalent to `.align` with a size of 2.
  `1`
    Align SPC to word boundary
  `2`
    Align SPC to longword boundary (same as .even)
  `128`
    Align SPC to page boundary

`.asg string, name`
  Assign name the string string. String replacement is performed on string before assignment.

`.eval string, name`
  Evaluate the contents of string string and assign the result as a string to the subsym name. String replacement is performed on string before assignment.

`.bss symbol, size [, [blocking_flag] [,alignment_flag]]`
  Reserve space for symbol in the .bss section. size is in words. If present, blocking_flag indicates the allocated space should be aligned on a page boundary if it would otherwise cross a page boundary. If present, alignment_flag causes the assembler to allocate size on a long word boundary.

`.byte value [,...,value_n]`
`.ubyte value [,...,value_n]`
`.char value [,...,value_n]`
`.uchar value [,...,value_n]`
  Place one or more bytes into consecutive words of the current section. The upper 8 bits of each word is zero-filled. If a label is used, it points to the word allocated for the first byte encountered.

`.clink ["section_name"]`
  Set STYP_CLINK flag for this section, which indicates to the linker that if no symbols from this section are referenced, the section should not be included in the link. If section_name is omitted, the current section is used.

`.c_mode`
  TBD.

`.copy "filename" | filename`
`.include "filename" | filename`
  Read source statements from filename. The normal include search path is used. Normally .copy will cause statements from the included file to be printed in the assembly listing and .include will not, but this distinction is not currently implemented.

`.data`
  Begin assembling code into the .data section.

`.double value [,...,value_n]`
`.ldouble value [,...,value_n]`
`.float value [,...,value_n]`
`.xfloat value [,...,value_n]`
  Place an IEEE single-precision floating-point representation of one or more floating-point values into the current section. All but `.xfloat` align the result on a longword boundary. Values are stored most-significant word first.

`.drlist`
`.drnolist`
  Control printing of directives to the listing file. Ignored.

`.emsg string`
`.mmsg string`
`.wmsg string`
  Emit a user-defined error, message, or warning, respectively.

`.far_mode`
  Use extended addressing when assembling statements. This should appear only once per file, and is equivalent to the -mfar-mode option see section `-mfar-mode`.

`.fclist`
`.fcnolist`
  Control printing of false conditional blocks to the listing file.

`.field value [,size]`
  Initialize a bitfield of size bits in the current section. If value is relocatable, then size must be 16. size defaults to 16 bits. If value does not fit into size bits, the value will be truncated. Successive `.field` directives will pack starting at the current word, filling the most significant bits first, and aligning to the start of the next word if the field size does not fit into the space remaining in the current word. A `.align` directive with an operand of 1 will force the next `.field` directive to begin packing into a new word. If a label is used, it points to the word that contains the specified field.

`.global symbol [,...,symbol_n]`
`.def symbol [,...,symbol_n]`
`.ref symbol [,...,symbol_n]`
  `.def` nominally identifies a symbol defined in the current file and available to other files. `.ref` identifies a symbol used in the current file but defined elsewhere. Both map to the standard `.global` directive.

`.half value [,...,value_n]`
`.uhalf value [,...,value_n]`
`.short value [,...,value_n]`
`.ushort value [,...,value_n]`
`.int value [,...,value_n]`
`.uint value [,...,value_n]`
`.word value [,...,value_n]`
`.uword value [,...,value_n]`
  Place one or more values into consecutive words of the current section. If a label is used, it points to the word allocated for the first value encountered.

`.label symbol`
  Define a special symbol to refer to the load time address of the current section program counter.

`.length`
`.width`
  Set the page length and width of the output listing file. Ignored.

`.list`
`.nolist`
  Control whether the source listing is printed. Ignored.

`.long value [,...,value_n]`
`.ulong value [,...,value_n]`
`.xlong value [,...,value_n]`
  Place one or more 32-bit values into consecutive words in the current section. The most significant word is stored first. `.long` and `.ulong` align the result on a longword boundary; `xlong` does not.

`.loop [count]`
`.break [condition]`
`.endloop`
  Repeatedly assemble a block of code. `.loop` begins the block, and `.endloop` marks its termination. count defaults to 1024, and indicates the number of times the block should be repeated. `.break` terminates the loop so that assembly begins after the `.endloop` directive. The optional condition will cause the loop to terminate only if it evaluates to zero.

`macro_name .macro [param1][,...param_n]`
`[.mexit]`
`.endm`
  See the section on macros for more explanation (See section 9.39.10 Macros.

`.mlib "filename" | filename`
  Load the macro library filename. filename must be an archived library (BFD ar-compatible) of text files, expected to contain only macro definitions. The standard include search path is used.

`.mlist`
`.mnolist`
  Control whether to include macro and loop block expansions in the listing output. Ignored.

`.mmregs`
  Define global symbolic names for the 'c54x registers. Supposedly equivalent to executing `.set` directives for each register with its memory-mapped value, but in reality is provided only for compatibility and does nothing.

`.newblock`
  This directive resets any TIC54X local labels currently defined. Normal `as` local labels are unaffected.

`.option option_list`
  Set listing options. Ignored.

`.sblock "section_name" | section_name [,"name_n" | name_n]`
  Designate section_name for blocking. Blocking guarantees that a section will start on a page boundary (128 words) if it would otherwise cross a page boundary. Only initialized sections may be designated with this directive. See also See section 9.39.2 Blocking.

`.sect "section_name"`
  Define a named initialized section and make it the current section.

`symbol .set "value"`
`symbol .equ "value"`
  Equate a constant value to a symbol, which is placed in the symbol table. symbol may not be previously defined.

`.space size_in_bits`
`.bes size_in_bits`
  Reserve the given number of bits in the current section and zero-fill them. If a label is used with `.space`, it points to the first word reserved. With `.bes`, the label points to the last word reserved.

`.sslist`
`.ssnolist`
  Controls the inclusion of subsym replacement in the listing output. Ignored.

`.string "string" [,...,"string_n"]`
`.pstring "string" [,...,"string_n"]`
  Place 8-bit characters from string into the current section. `.string` zero-fills the upper 8 bits of each word, while `.pstring` puts two characters into each word, filling the most-significant bits first. Unused space is zero-filled. If a label is used, it points to the first word initialized.

`[stag] .struct [offset]`
`[name_1] element [count_1]`
`[name_2] element [count_2]`
`[tname] .tag stagx [tcount]`
`...`
`[name_n] element [count_n]`
`[ssize] .endstruct`
`label .tag [stag]`
  Assign symbolic offsets to the elements of a structure. stag defines a symbol to use to reference the structure. offset indicates a starting value to use for the first element encountered; otherwise it defaults to zero. Each element can have a named offset, name, which is a symbol assigned the value of the element's offset into the structure. If stag is missing, these become global symbols. count adjusts the offset that many times, as if `element` were an array. `element` may be one of `.byte`, `.word`, `.long`, `.float`, or any equivalent of those, and the structure offset is adjusted accordingly. `.field` and `.string` are also allowed; the size of `.field` is one bit, and `.string` is considered to be one word in size. Only element descriptors, structure/union tags, `.align` and conditional assembly directives are allowed within `.struct`/`.endstruct`. `.align` aligns member offsets to word boundaries only. ssize, if provided, will always be assigned the size of the structure.

  The `.tag` directive, in addition to being used to define a structure/union element within a structure, may be used to apply a structure to a symbol. Once applied to label, the individual structure elements may be applied to label to produce the desired offsets using label as the structure base.

`.tab`
  Set the tab size in the output listing. Ignored.

`[utag] .union`
`[name_1] element [count_1]`
`[name_2] element [count_2]`
`[tname] .tag utagx[,tcount]`
`...`
`[name_n] element [count_n]`
`[usize] .endstruct`
`label .tag [utag]`
  Similar to `.struct`, but the offset after each element is reset to zero, and the usize is set to the maximum of all defined elements. Starting offset for the union is always zero.

`[symbol] .usect "section_name", size, [,[blocking_flag] [,alignment_flag]]`
  Reserve space for variables in a named, uninitialized section (similar to .bss). `.usect` allows definitions sections independent of .bss. symbol points to the first location reserved by this allocation. The symbol may be used as a variable name. size is the allocated size in words. blocking_flag indicates whether to block this section on a page boundary (128 words) (see section 9.39.2 Blocking). alignment flag indicates whether the section should be longword-aligned.

`.var sym[,..., sym_n]`
  Define a subsym to be a local variable within a macro. See See section 9.39.10 Macros.

`.version version`
  Set which processor to build instructions for. Though the following values are accepted, the op is ignored.
  `541`
  `542`
  `543`
  `545`
  `545LP`
  `546LP`
  `548`
  `549`

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### 9.39.10 Macros

Macros do not require explicit dereferencing of arguments (i.e., \ARG).

During macro expansion, the macro parameters are converted to subsyms. If the number of arguments passed the macro invocation exceeds the number of parameters defined, the last parameter is assigned the string equivalent of all remaining arguments. If fewer arguments are given than parameters, the missing parameters are assigned empty strings. To include a comma in an argument, you must enclose the argument in quotes.

The following built-in subsym functions allow examination of the string value of subsyms (or ordinary strings). The arguments are strings unless otherwise indicated (subsyms passed as args will be replaced by the strings they represent).

``$symlen(str)``
  Returns the length of str.

``$symcmp(str1,str2)``
  Returns 0 if str1 == str2, non-zero otherwise.

``$firstch(str,ch)``
  Returns index of the first occurrence of character constant ch in str.

``$lastch(str,ch)``
  Returns index of the last occurrence of character constant ch in str.

``$isdefed(symbol)``
  Returns zero if the symbol symbol is not in the symbol table, non-zero otherwise.

``$ismember(symbol,list)``
  Assign the first member of comma-separated string list to symbol; list is reassigned the remainder of the list. Returns zero if list is a null string. Both arguments must be subsyms.

``$iscons(expr)``
  Returns 1 if string expr is binary, 2 if octal, 3 if hexadecimal, 4 if a character, 5 if decimal, and zero if not an integer.

``$isname(name)``
  Returns 1 if name is a valid symbol name, zero otherwise.

``$isreg(reg)``
  Returns 1 if reg is a valid predefined register name (AR0-AR7 only).

``$structsz(stag)``
  Returns the size of the structure or union represented by stag.

``$structacc(stag)``
  Returns the reference point of the structure or union represented by stag. Always returns zero.

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### 9.39.11 Memory-mapped Registers

The following symbols are recognized as memory-mapped registers:

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### 9.39.12 TIC54X Syntax

> 9.39.12.1 Special Characters |  |

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#### 9.39.12.1 Special Characters

The presence of a ``;'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The presence of an asterisk (``*'`) at the start of a line also indicates a comment that extends to the end of that line.

The TIC54X assembler does not currently support a line separator character.

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## 9.40 TIC6X Dependent Features

> 9.40.1 TIC6X Options |  | Options
> 9.40.2 TIC6X Syntax |  | Syntax
> 9.40.3 TIC6X Directives |  | Directives

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### 9.40.1 TIC6X Options

`-march=arch`
  Enable (only) instructions from architecture arch. By default, all instructions are permitted.

  The following values of arch are accepted: `c62x`, `c64x`, `c64x+`, `c67x`, `c67x+`, `c674x`.

`-mdsbt`
`-mno-dsbt`
  The ``-mdsbt'` option causes the assembler to generate the `Tag_ABI_DSBT` attribute with a value of 1, indicating that the code is using DSBT addressing. The ``-mno-dsbt'` option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non-DSBT) are linked together.

`-mpid=no`
`-mpid=near`
`-mpid=far`
  The ``-mpid='` option causes the assembler to generate the `Tag_ABI_PID` attribute with a value indicating the form of data addressing used by the code. ``-mpid=no'`, the default, indicates position-dependent data addressing, ``-mpid=near'` indicates position-independent addressing with GOT accesses using near DP addressing, and ``-mpid=far'` indicates position-independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together.

`-mpic`
`-mno-pic`
  The ``-mpic'` option causes the assembler to generate the `Tag_ABI_PIC` attribute with a value of 1, indicating that the code is using position-independent code addressing, The `-mno-pic` option, the default, causes the tag to have a value of 0, indicating position-dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together.

`-mbig-endian`
`-mlittle-endian`
  Generate code for the specified endianness. The default is little-endian.

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### 9.40.2 TIC6X Syntax

The presence of a ``;'` on a line indicates the start of a comment that extends to the end of the current line. If a ``#'` or ``*'` appears as the first character of a line, the whole line is treated as a comment. Note that if a line starts with a ``#'` character then it can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``@'` character can be used instead of a newline to separate statements.

Instruction, register and functional unit names are case-insensitive. `as` requires fully-specified functional unit names, such as ``.S1'`, ``.L1X'` or ``.D1T2'`, on all instructions using a functional unit.

For some instructions, there may be syntactic ambiguity between register or functional unit names and the names of labels or other symbols. To avoid this, enclose the ambiguous symbol name in parentheses; register and functional unit names may not be enclosed in parentheses.

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### 9.40.3 TIC6X Directives

Directives controlling the set of instructions accepted by the assembler have effect for instructions between the directive and any subsequent directive overriding it.

`.arch arch`
  This has the same effect as ``-march=arch'`.

`.cantunwind`
  Prevents unwinding through the current function. No personality routine or exception table data is required or permitted.

  If this is not specified then frame unwinding information will be constructed from CFI directives. see section 7.11 `.cfi_sections section_list`.

`.c6xabi_attribute tag, value`
  Set the C6000 EABI build attribute tag to value.

  The tag is either an attribute number or one of `Tag_ISA`, `Tag_ABI_wchar_t`, `Tag_ABI_stack_align_needed`, `Tag_ABI_stack_align_preserved`, `Tag_ABI_DSBT`, `Tag_ABI_PID`, `Tag_ABI_PIC`, `TAG_ABI_array_object_alignment`, `TAG_ABI_array_object_align_expected`, `Tag_ABI_compatibility` and `Tag_ABI_conformance`. The value is either a `number`, `"string"`, or `number, "string"` depending on the tag.

`.ehtype symbol`
  Output an exception type table reference to symbol.

`.endp`
  Marks the end of and exception table or function. If preceeded by a `.handlerdata` directive then this also switched back to the previous text section.

`.handlerdata`
  Marks the end of the current function, and the start of the exception table entry for that function. Anything between this directive and the `.endp` directive will be added to the exception table entry.

  Must be preceded by a CFI block containing a `.cfi_lsda` directive.

`.nocmp`
  Disallow use of C64x+ compact instructions in the current text section.

`.personalityindex index`
  Sets the personality routine for the current function to the ABI specified compact routine number index

`.personality name`
  Sets the personality routine for the current function to name.

`.scomm symbol, size, align`
  Like `.comm`, creating a common symbol symbol with size size and alignment align, but unlike when using `.comm`, this symbol will be placed into the small BSS section by the linker.

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## 9.41 TILE-Gx Dependent Features

> 9.41.1 Options |  | TILE-Gx Options
> 9.41.2 Syntax |  | TILE-Gx Syntax
> 9.41.3 TILE-Gx Directives |  |

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### 9.41.1 Options

The following table lists all available TILE-Gx specific options:

`-m32 | -m64`
  Select the word size, either 32 bits or 64 bits.

`-EB | -EL`
  Select the endianness, either big-endian (-EB) or little-endian (-EL).

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### 9.41.2 Syntax

Block comments are delimited by ``/*'` and ``*/'`. End of line comments may be introduced by ``#'`.

Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:

    opcode [operand, ...]

Instructions must be separated by a newline or semicolon.

There are two ways to write code: either write naked instructions, which the assembler is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.

Bundles are specified using curly braces:

    { add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }

A bundle can span multiple lines. If you want to put multiple instructions on a line, whether in a bundle or not, you need to separate them with semicolons as in this example.

A bundle may contain one or more instructions, up to the limit specified by the ISA (currently three). If fewer instructions are specified than the hardware supports in a bundle, the assembler inserts `fnop` instructions automatically.

The assembler will prefer to preserve the ordering of instructions within the bundle, putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact, combined with the optional use of explicit `fnop` or `nop` instructions, allows precise control over which pipeline executes each instruction.

If the instructions cannot be bundled in the listed order, the assembler will automatically try to find a valid pipeline assignment. If there is no way to bundle the instructions together, the assembler reports an error.

The assembler does not yet auto-bundle (automatically combine multiple instructions into one bundle), but it reserves the right to do so in the future. If you want to force an instruction to run by itself, put it in a bundle explicitly with curly braces and use `nop` instructions (not `fnop`) to fill the remaining pipeline slots in that bundle.

> 9.41.2.1 Opcode Names |  | Opcode Naming Conventions.
> 9.41.2.2 Register Names |  | Register Naming.
> 9.41.2.3 Symbolic Operand Modifiers |  |

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#### 9.41.2.1 Opcode Names

For a complete list of opcodes and descriptions of their semantics, see TILE-Gx Instruction Set Architecture, available upon request at www.tilera.com.

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#### 9.41.2.2 Register Names

General-purpose registers are represented by predefined symbols of the form ``rN'`, where N represents a number between `0` and `63`. However, the following registers have canonical names that must be used instead:

`r54`
  sp

`r55`
  lr

`r56`
  sn

`r57`
  idn0

`r58`
  idn1

`r59`
  udn0

`r60`
  udn1

`r61`
  udn2

`r62`
  udn3

`r63`
  zero

The assembler will emit a warning if a numeric name is used instead of the non-numeric name. The `.no_require_canonical_reg_names` assembler pseudo-op turns off this warning. `.require_canonical_reg_names` turns it back on.

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#### 9.41.2.3 Symbolic Operand Modifiers

The assembler supports several modifiers when using symbol addresses in TILE-Gx instruction operands. The general syntax is the following:

    modifier(symbol)

The following modifiers are supported:

`hw0`

  This modifier is used to load bits 0-15 of the symbol's address.

`hw1`

  This modifier is used to load bits 16-31 of the symbol's address.

`hw2`

  This modifier is used to load bits 32-47 of the symbol's address.

`hw3`

  This modifier is used to load bits 48-63 of the symbol's address.

`hw0_last`

  This modifier yields the same value as `hw0`, but it also checks that the value does not overflow.

`hw1_last`

  This modifier yields the same value as `hw1`, but it also checks that the value does not overflow.

`hw2_last`

  This modifier yields the same value as `hw2`, but it also checks that the value does not overflow.

  A 48-bit symbolic value is constructed by using the following idiom:

      moveli r0, hw2_last(sym)
      shl16insli r0, r0, hw1(sym)
      shl16insli r0, r0, hw0(sym)

`hw0_got`

  This modifier is used to load bits 0-15 of the symbol's offset in the GOT entry corresponding to the symbol.

`hw0_last_got`

  This modifier yields the same value as `hw0_got`, but it also checks that the value does not overflow.

`hw1_last_got`

  This modifier is used to load bits 16-31 of the symbol's offset in the GOT entry corresponding to the symbol, and it also checks that the value does not overflow.

`plt`

  This modifier is used for function symbols. It causes a procedure linkage table, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to look up and set the value of the symbol the first time the function is called (at latest; depending environment variables). It is only safe to leave the symbol unresolved this way if all references are function calls.

`hw0_plt`

  This modifier is used to load bits 0-15 of the pc-relative address of a plt entry.

`hw1_plt`

  This modifier is used to load bits 16-31 of the pc-relative address of a plt entry.

`hw1_last_plt`

  This modifier yields the same value as `hw1_plt`, but it also checks that the value does not overflow.

`hw2_last_plt`

  This modifier is used to load bits 32-47 of the pc-relative address of a plt entry, and it also checks that the value does not overflow.

`hw0_tls_gd`

  This modifier is used to load bits 0-15 of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses.

`hw0_last_tls_gd`

  This modifier yields the same value as `hw0_tls_gd`, but it also checks that the value does not overflow.

`hw1_last_tls_gd`

  This modifier is used to load bits 16-31 of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses. It also checks that the value does not overflow.

`hw0_tls_ie`

  This modifier is used to load bits 0-15 of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses.

`hw0_last_tls_ie`

  This modifier yields the same value as `hw0_tls_ie`, but it also checks that the value does not overflow.

`hw1_last_tls_ie`

  This modifier is used to load bits 16-31 of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses. It also checks that the value does not overflow.

`hw0_tls_le`

  This modifier is used to load bits 0-15 of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses.

`hw0_last_tls_le`

  This modifier yields the same value as `hw0_tls_le`, but it also checks that the value does not overflow.

`hw1_last_tls_le`

  This modifier is used to load bits 16-31 of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses. It also checks that the value does not overflow.

`tls_gd_call`

  This modifier is used to tag an instrution as the "call" part of a calling sequence for a TLS GD reference of its operand.

`tls_gd_add`

  This modifier is used to tag an instruction as the "add" part of a calling sequence for a TLS GD reference of its operand.

`tls_ie_load`

  This modifier is used to tag an instruction as the "load" part of a calling sequence for a TLS IE reference of its operand.

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### 9.41.3 TILE-Gx Directives

`.align expression [, expression]`
  This is the generic .align directive. The first argument is the requested alignment in bytes.

`.allow_suspicious_bundles`
  Turns on error checking for combinations of instructions in a bundle that probably indicate a programming error. This is on by default.

`.no_allow_suspicious_bundles`
  Turns off error checking for combinations of instructions in a bundle that probably indicate a programming error.

`.require_canonical_reg_names`
  Require that canonical register names be used, and emit a warning if the numeric names are used. This is on by default.

`.no_require_canonical_reg_names`
  Permit the use of numeric names for registers that have canonical names.

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## 9.42 TILEPro Dependent Features

> 9.42.1 Options |  | TILEPro Options
> 9.42.2 Syntax |  | TILEPro Syntax
> 9.42.3 TILEPro Directives |  |

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### 9.42.1 Options

`as` has no machine-dependent command-line options for TILEPro.

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### 9.42.2 Syntax

Block comments are delimited by ``/*'` and ``*/'`. End of line comments may be introduced by ``#'`.

Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:

    opcode [operand, ...]

Instructions must be separated by a newline or semicolon.

There are two ways to write code: either write naked instructions, which the assembler is free to combine into VLIW bundles, or specify the VLIW bundles explicitly.

Bundles are specified using curly braces:

    { add r3,r4,r5 ; add r7,r8,r9 ; lw r10,r11 }

A bundle can span multiple lines. If you want to put multiple instructions on a line, whether in a bundle or not, you need to separate them with semicolons as in this example.

A bundle may contain one or more instructions, up to the limit specified by the ISA (currently three). If fewer instructions are specified than the hardware supports in a bundle, the assembler inserts `fnop` instructions automatically.

The assembler will prefer to preserve the ordering of instructions within the bundle, putting the first instruction in a lower-numbered pipeline than the next one, etc. This fact, combined with the optional use of explicit `fnop` or `nop` instructions, allows precise control over which pipeline executes each instruction.

If the instructions cannot be bundled in the listed order, the assembler will automatically try to find a valid pipeline assignment. If there is no way to bundle the instructions together, the assembler reports an error.

The assembler does not yet auto-bundle (automatically combine multiple instructions into one bundle), but it reserves the right to do so in the future. If you want to force an instruction to run by itself, put it in a bundle explicitly with curly braces and use `nop` instructions (not `fnop`) to fill the remaining pipeline slots in that bundle.

> 9.42.2.1 Opcode Names |  | Opcode Naming Conventions.
> 9.42.2.2 Register Names |  | Register Naming.
> 9.42.2.3 Symbolic Operand Modifiers |  |

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#### 9.42.2.1 Opcode Names

For a complete list of opcodes and descriptions of their semantics, see TILE Processor User Architecture Manual, available upon request at www.tilera.com.

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#### 9.42.2.2 Register Names

General-purpose registers are represented by predefined symbols of the form ``rN'`, where N represents a number between `0` and `63`. However, the following registers have canonical names that must be used instead:

`r54`
  sp

`r55`
  lr

`r56`
  sn

`r57`
  idn0

`r58`
  idn1

`r59`
  udn0

`r60`
  udn1

`r61`
  udn2

`r62`
  udn3

`r63`
  zero

The assembler will emit a warning if a numeric name is used instead of the canonical name. The `.no_require_canonical_reg_names` assembler pseudo-op turns off this warning. `.require_canonical_reg_names` turns it back on.

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#### 9.42.2.3 Symbolic Operand Modifiers

The assembler supports several modifiers when using symbol addresses in TILEPro instruction operands. The general syntax is the following:

    modifier(symbol)

The following modifiers are supported:

`lo16`

  This modifier is used to load the low 16 bits of the symbol's address, sign-extended to a 32-bit value (sign-extension allows it to be range-checked against signed 16 bit immediate operands without complaint).

`hi16`

  This modifier is used to load the high 16 bits of the symbol's address, also sign-extended to a 32-bit value.

`ha16`

  `ha16(N)` is identical to `hi16(N)`, except if `lo16(N)` is negative it adds one to the `hi16(N)` value. This way `lo16` and `ha16` can be added to create any 32-bit value using `auli`. For example, here is how you move an arbitrary 32-bit address into r3:

      moveli r3, lo16(sym)
      auli r3, r3, ha16(sym)

`got`

  This modifier is used to load the offset of the GOT entry corresponding to the symbol.

`got_lo16`

  This modifier is used to load the sign-extended low 16 bits of the offset of the GOT entry corresponding to the symbol.

`got_hi16`

  This modifier is used to load the sign-extended high 16 bits of the offset of the GOT entry corresponding to the symbol.

`got_ha16`

  This modifier is like `got_hi16`, but it adds one if `got_lo16` of the input value is negative.

`plt`

  This modifier is used for function symbols. It causes a procedure linkage table, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to look up and set the value of the symbol the first time the function is called (at latest; depending environment variables). It is only safe to leave the symbol unresolved this way if all references are function calls.

`tls_gd`

  This modifier is used to load the offset of the GOT entry of the symbol's TLS descriptor, to be used for general-dynamic TLS accesses.

`tls_gd_lo16`

  This modifier is used to load the sign-extended low 16 bits of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general dynamic TLS accesses.

`tls_gd_hi16`

  This modifier is used to load the sign-extended high 16 bits of the offset of the GOT entry of the symbol's TLS descriptor, to be used for general dynamic TLS accesses.

`tls_gd_ha16`

  This modifier is like `tls_gd_hi16`, but it adds one to the value if `tls_gd_lo16` of the input value is negative.

`tls_ie`

  This modifier is used to load the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses.

`tls_ie_lo16`

  This modifier is used to load the low 16 bits of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses.

`tls_ie_hi16`

  This modifier is used to load the high 16 bits of the offset of the GOT entry containing the offset of the symbol's address from the TCB, to be used for initial-exec TLS accesses.

`tls_ie_ha16`

  This modifier is like `tls_ie_hi16`, but it adds one to the value if `tls_ie_lo16` of the input value is negative.

`tls_le`

  This modifier is used to load the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses.

`tls_le_lo16`

  This modifier is used to load the low 16 bits of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses.

`tls_le_hi16`

  This modifier is used to load the high 16 bits of the offset of the symbol's address from the TCB, to be used for local-exec TLS accesses.

`tls_le_ha16`

  This modifier is like `tls_le_hi16`, but it adds one to the value if `tls_le_lo16` of the input value is negative.

`tls_gd_call`

  This modifier is used to tag an instrution as the "call" part of a calling sequence for a TLS GD reference of its operand.

`tls_gd_add`

  This modifier is used to tag an instruction as the "add" part of a calling sequence for a TLS GD reference of its operand.

`tls_ie_load`

  This modifier is used to tag an instruction as the "load" part of a calling sequence for a TLS IE reference of its operand.

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### 9.42.3 TILEPro Directives

`.align expression [, expression]`
  This is the generic .align directive. The first argument is the requested alignment in bytes.

`.allow_suspicious_bundles`
  Turns on error checking for combinations of instructions in a bundle that probably indicate a programming error. This is on by default.

`.no_allow_suspicious_bundles`
  Turns off error checking for combinations of instructions in a bundle that probably indicate a programming error.

`.require_canonical_reg_names`
  Require that canonical register names be used, and emit a warning if the numeric names are used. This is on by default.

`.no_require_canonical_reg_names`
  Permit the use of numeric names for registers that have canonical names.

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## 9.43 Z80 Dependent Features

> 9.43.1 Options |  |
> 9.43.2 Syntax |  |
> 9.43.3 Floating Point |  |
> 9.43.4 Z80 Assembler Directives |  | Z80 Machine Directives
> 9.43.5 Opcodes |  |

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### 9.43.1 Options

The Zilog Z80 and Ascii R800 version of `as` have a few machine dependent options.

``-z80'`
  Produce code for the Z80 processor. There are additional options to request warnings and error messages for undocumented instructions.
``-ignore-undocumented-instructions'`
``-Wnud'`
  Silently assemble undocumented Z80-instructions that have been adopted as documented R800-instructions.
``-ignore-unportable-instructions'`
``-Wnup'`
  Silently assemble all undocumented Z80-instructions.
``-warn-undocumented-instructions'`
``-Wud'`
  Issue warnings for undocumented Z80-instructions that work on R800, do not assemble other undocumented instructions without warning.
``-warn-unportable-instructions'`
``-Wup'`
  Issue warnings for other undocumented Z80-instructions, do not treat any undocumented instructions as errors.
``-forbid-undocumented-instructions'`
``-Fud'`
  Treat all undocumented z80-instructions as errors.
``-forbid-unportable-instructions'`
``-Fup'`
  Treat undocumented z80-instructions that do not work on R800 as errors.

``-r800'`
  Produce code for the R800 processor. The assembler does not support undocumented instructions for the R800. In line with common practice, `as` uses Z80 instruction names for the R800 processor, as far as they exist.

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### 9.43.2 Syntax

The assembler syntax closely follows the 'Z80 family CPU User Manual' by Zilog. In expressions a single ``='` may be used as "is equal to" comparison operator.

Suffices can be used to indicate the radix of integer constants; ``H'` or ``h'` for hexadecimal, ``D'` or ``d'` for decimal, ``Q'`, ``O'`, ``q'` or ``o'` for octal, and ``B'` for binary.

The suffix ``b'` denotes a backreference to local label.

> 9.43.2.1 Special Characters |  |
> 9.43.2.2 Register Names |  |
> 9.43.2.3 Case Sensitivity |  |

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#### 9.43.2.1 Special Characters

The semicolon ``;'` is the line comment character;

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The Z80 assembler does not support a line separator character.

The dollar sign ``$'` can be used as a prefix for hexadecimal numbers and as a symbol denoting the current location counter.

A backslash ``\'` is an ordinary character for the Z80 assembler.

The single quote ``''` must be followed by a closing quote. If there is one character in between, it is a character constant, otherwise it is a string constant.

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#### 9.43.2.2 Register Names

The registers are referred to with the letters assigned to them by Zilog. In addition `as` recognizes ``ixl'` and ``ixh'` as the least and most significant octet in ``ix'`, and similarly ``iyl'` and ``iyh'` as parts of ``iy'`.

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#### 9.43.2.3 Case Sensitivity

Upper and lower case are equivalent in register names, opcodes, condition codes and assembler directives. The case of letters is significant in labels and symbol names. The case is also important to distinguish the suffix ``b'` for a backward reference to a local label from the suffix ``B'` for a number in binary notation.

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### 9.43.3 Floating Point

Floating-point numbers are not supported.

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### 9.43.4 Z80 Assembler Directives

`as` for the Z80 supports some additional directives for compatibility with other assemblers.

These are the additional directives in `as` for the Z80:

`db expression|string[,expression|string...]`
`defb expression|string[,expression|string...]`
  For each string the characters are copied to the object file, for each other expression the value is stored in one byte. A warning is issued in case of an overflow.

`dw expression[,expression...]`
`defw expression[,expression...]`
  For each expression the value is stored in two bytes, ignoring overflow.

`d24 expression[,expression...]`
`def24 expression[,expression...]`
  For each expression the value is stored in three bytes, ignoring overflow.

`d32 expression[,expression...]`
`def32 expression[,expression...]`
  For each expression the value is stored in four bytes, ignoring overflow.

`ds count[, value]`
`defs count[, value]`
  Fill count bytes in the object file with value, if value is omitted it defaults to zero.

`symbol equ expression`
`symbol defl expression`
  These directives set the value of symbol to expression. If `equ` is used, it is an error if symbol is already defined. Symbols defined with `equ` are not protected from redefinition.

`set`
  This is a normal instruction on Z80, and not an assembler directive.

`psect name`
  A synonym for See section 7.99 `.section name`, no second argument should be given.

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### 9.43.5 Opcodes

In line with common practice, Z80 mnemonics are used for both the Z80 and the R800.

In many instructions it is possible to use one of the half index registers (``ixl'`,``ixh'`,``iyl'`,``iyh'`) in stead of an 8-bit general purpose register. This yields instructions that are documented on the R800 and undocumented on the Z80. Similarly `in f,(c)` is documented on the R800 and undocumented on the Z80.

The assembler also supports the following undocumented Z80-instructions, that have not been adopted in the R800 instruction set:

`out (c),0`
  Sends zero to the port pointed to by register c.

`sli m`
  Equivalent to `m = (m<<1)+1`, the operand m can be any operand that is valid for ``sla'`. One can use ``sll'` as a synonym for ``sli'`.

`op (ix+d), r`
  This is equivalent to

      ld r, (ix+d)
      opc r
      ld (ix+d), r

  The operation ``opc'` may be any of ``res b,'`, ``set b,'`, ``rl'`, ``rlc'`, ``rr'`, ``rrc'`, ``sla'`, ``sli'`, ``sra'` and ``srl'`, and the register ``r'` may be any of ``a'`, ``b'`, ``c'`, ``d'`, ``e'`, ``h'` and ``l'`.

`opc (iy+d), r`
  As above, but with ``iy'` instead of ``ix'`.

The web site at http://www.z80.info is a good starting place to find more information on programming the Z80.

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## 9.44 Z8000 Dependent Features

The Z8000 as supports both members of the Z8000 family: the unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 24 bit addresses.

When the assembler is in unsegmented mode (specified with the `unsegm` directive), an address takes up one word (16 bit) sized register. When the assembler is in segmented mode (specified with the `segm` directive), a 24-bit address takes up a long (32 bit) register. See section Assembler Directives for the Z8000, for a list of other Z8000 specific assembler directives.

> 9.44.1 Options |  | Command-line options for the Z8000
> 9.44.2 Syntax |  | Assembler syntax for the Z8000
> 9.44.3 Assembler Directives for the Z8000 |  | Special directives for the Z8000
> 9.44.4 Opcodes |  |

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### 9.44.1 Options

``-z8001'`
  Generate segmented code by default.

``-z8002'`
  Generate unsegmented code by default.

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### 9.44.2 Syntax

> 9.44.2.1 Special Characters |  |
> 9.44.2.2 Register Names |  |
> 9.44.2.3 Addressing Modes |  |

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#### 9.44.2.1 Special Characters

``!'` is the line comment character.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

You can use ``;'` instead of a newline to separate statements.

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#### 9.44.2.2 Register Names

The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer to different sized groups of registers by register number, with the prefix ``r'` for 16 bit registers, ``rr'` for 32 bit registers and ``rq'` for 64 bit registers. You can also refer to the contents of the first eight (of the sixteen 16 bit registers) by bytes. They are named ``rln'` and ``rhn'`.

    byte registers
    rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
    rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7

    word registers
    r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

    long word registers
    rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14

    quad word registers
    rq0 rq4 rq8 rq12

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#### 9.44.2.3 Addressing Modes

as understands the following addressing modes for the Z8000:

`rln`
`rhn`
`rn`
`rrn`
`rqn`
  Register direct: 8bit, 16bit, 32bit, and 64bit registers.

`@rn`
`@rrn`
  Indirect register: @rrn in segmented mode, @rn in unsegmented mode.

`addr`
  Direct: the 16 bit or 24 bit address (depending on whether the assembler is in segmented or unsegmented mode) of the operand is in the instruction.

`address(rn)`
  Indexed: the 16 or 24 bit address is added to the 16 bit register to produce the final address in memory of the operand.

`rn(#imm)`
`rrn(#imm)`
  Base Address: the 16 or 24 bit register is added to the 16 bit sign extended immediate displacement to produce the final address in memory of the operand.

`rn(rm)`
`rrn(rm)`
  Base Index: the 16 or 24 bit register rn or rrn is added to the sign extended 16 bit index register rm to produce the final address in memory of the operand.

`#xx`
  Immediate data xx.

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### 9.44.3 Assembler Directives for the Z8000

The Z8000 port of as includes additional assembler directives, for compatibility with other Z8000 assemblers. These do not begin with ``.'` (unlike the ordinary as directives).

`segm`
`.z8001`
  Generate code for the segmented Z8001.

`unsegm`
`.z8002`
  Generate code for the unsegmented Z8002.

`name`
  Synonym for `.file`

`global`
  Synonym for `.global`

`wval`
  Synonym for `.word`

`lval`
  Synonym for `.long`

`bval`
  Synonym for `.byte`

`sval`
  Assemble a string. `sval` expects one string literal, delimited by single quotes. It assembles each byte of the string into consecutive addresses. You can use the escape sequence ``%xx'` (where xx represents a two-digit hexadecimal number) to represent the character whose ASCII value is xx. Use this feature to describe single quote and other characters that may not appear in string literals as themselves. For example, the C statement ``char *a = "he said \"it's 50% off\"";'` is represented in Z8000 assembly language (shown with the assembler output in hex at the left) as

      68652073    sval    'he said %22it%27s 50%25 off%22%00'
      61696420
      22697427
      73203530
      25206F66
      662200

`rsect`
  synonym for `.section`

`block`
  synonym for `.space`

`even`
  special case of `.align`; aligns output to even byte boundary.

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### 9.44.4 Opcodes

For detailed information on the Z8000 machine instruction set, see Z8000 Technical Manual.

The following table summarizes the opcodes and their arguments:

                rs   16 bit source register
                rd   16 bit destination register
                rbs   8 bit source register
                rbd   8 bit destination register
                rrs   32 bit source register
                rrd   32 bit destination register
                rqs   64 bit source register
                rqd   64 bit destination register
                addr 16/24 bit address
                imm  immediate data

    adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
    adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
    add rd,@rs              clrb rbd                dab rbd
    add rd,addr             com @rd                 dbjnz rbd,disp7
    add rd,addr(rs)         com addr                dec @rd,imm4m1
    add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
    add rd,rs               com rd                  dec addr,imm4m1
    addb rbd,@rs            comb @rd                dec rd,imm4m1
    addb rbd,addr           comb addr               decb @rd,imm4m1
    addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
    addb rbd,imm8           comb rbd                decb addr,imm4m1
    addb rbd,rbs            comflg flags            decb rbd,imm4m1
    addl rrd,@rs            cp @rd,imm16            di i2
    addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
    addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
    addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
    addl rrd,rrs            cp rd,addr              div rrd,imm16
    and rd,@rs              cp rd,addr(rs)          div rrd,rs
    and rd,addr             cp rd,imm16             divl rqd,@rs
    and rd,addr(rs)         cp rd,rs                divl rqd,addr
    and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
    and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
    andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
    andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
    andb rbd,addr(rs)       cpb rbd,addr            ei i2
    andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
    andb rbd,rbs            cpb rbd,imm8            ex rd,addr
    bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
    bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
    bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
    bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
    bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
    bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
    bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
    bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
    bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
    bitb rbd,rs             cpl rrd,@rs             ext8f imm8
    bpt                     cpl rrd,addr            exts rrd
    call @rd                cpl rrd,addr(rs)        extsb rd
    call addr               cpl rrd,imm32           extsl rqd
    call addr(rd)           cpl rrd,rrs             halt
    calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
    clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
    clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
    clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
    clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
    clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
    inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
    inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
    incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
    incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
    incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
    incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
    ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
    indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
    inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
    inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
    iret                    ldib @rd,@rs,rr         neg addr(rd)
    jp cc,@rd               ldir @rd,@rs,rr         neg rd
    jp cc,addr              ldirb @rd,@rs,rr        negb @rd
    jp cc,addr(rd)          ldk rd,imm4             negb addr
    jr cc,disp8             ldl @rd,rrs             negb addr(rd)
    ld @rd,imm16            ldl addr(rd),rrs        negb rbd
    ld @rd,rs               ldl addr,rrs            nop
    ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
    ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
    ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
    ld addr,rs              ldl rrd,addr            or rd,imm16
    ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
    ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
    ld rd,@rs               ldl rrd,rrs             orb rbd,addr
    ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
    ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
    ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
    ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
    ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
    ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
    lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
    lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
    lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
    lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
    ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
    ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
    ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
    ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
    ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
    ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
    ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
    ldb rbd,@rs             mbit                    popl addr,@rs
    ldb rbd,addr            mreq rd                 popl rrd,@rs
    ldb rbd,addr(rs)        mres                    push @rd,@rs
    ldb rbd,imm8            mset                    push @rd,addr
    ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
    ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
    push @rd,rs             set addr,imm4           subl rrd,imm32
    pushl @rd,@rs           set rd,imm4             subl rrd,rrs
    pushl @rd,addr          set rd,rs               tcc cc,rd
    pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
    pushl @rd,rrs           setb addr(rd),imm4      test @rd
    res @rd,imm4            setb addr,imm4          test addr
    res addr(rd),imm4       setb rbd,imm4           test addr(rd)
    res addr,imm4           setb rbd,rs             test rd
    res rd,imm4             setflg imm4             testb @rd
    res rd,rs               sinb rbd,imm16          testb addr
    resb @rd,imm4           sinb rd,imm16           testb addr(rd)
    resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
    resb addr,imm4          sindb @rd,@rs,rba       testl @rd
    resb rbd,imm4           sinib @rd,@rs,ra        testl addr
    resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
    resflg imm4             sla rd,imm8             testl rrd
    ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
    rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
    rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
    rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
    rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
    rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
    rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
    rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
    rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
    rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
    rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
    rsvd36                  sra rd,imm8             tset rd
    rsvd38                  srab rbd,imm8           tsetb @rd
    rsvd78                  sral rrd,imm8           tsetb addr
    rsvd7e                  srl rd,imm8             tsetb addr(rd)
    rsvd9d                  srlb rbd,imm8           tsetb rbd
    rsvd9f                  srll rrd,imm8           xor rd,@rs
    rsvdb9                  sub rd,@rs              xor rd,addr
    rsvdbf                  sub rd,addr             xor rd,addr(rs)
    sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
    sbcb rbd,rbs            sub rd,imm16            xor rd,rs
    sc imm8                 sub rd,rs               xorb rbd,@rs
    sda rd,rs               subb rbd,@rs            xorb rbd,addr
    sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
    sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
    sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
    sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
    sdll rrd,rs             subl rrd,@rs
    set @rd,imm4            subl rrd,addr
    set addr(rd),imm4       subl rrd,addr(rs)

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## 9.45 VAX Dependent Features

> 9.45.1 VAX Command-Line Options |  |
> 9.45.2 VAX Floating Point |  |
> 9.45.3 Vax Machine Directives |  |
> 9.45.4 VAX Opcodes |  |
> 9.45.5 VAX Branch Improvement |  |
> 9.45.6 VAX Operands |  |
> 9.45.7 Not Supported on VAX |  |
> 9.45.8 VAX Syntax |  |

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### 9.45.1 VAX Command-Line Options

The Vax version of `as` accepts any of the following options, gives a warning message that the option was ignored and proceeds. These options are for compatibility with scripts designed for other people's assemblers.

``-D` (Debug)`
``-S` (Symbol Table)`
``-T` (Token Trace)`
  These are obsolete options used to debug old assemblers.

``-d` (Displacement size for JUMPs)`
  This option expects a number following the ``-d'`. Like options that expect filenames, the number may immediately follow the ``-d'` (old standard) or constitute the whole of the command line argument that follows ``-d'` (GNU standard).

``-V` (Virtualize Interpass Temporary File)`
  Some other assemblers use a temporary file. This option commanded them to keep the information in active memory rather than in a disk file. `as` always does this, so this option is redundant.

``-J` (JUMPify Longer Branches)`
  Many 32-bit computers permit a variety of branch instructions to do the same job. Some of these instructions are short (and fast) but have a limited range; others are long (and slow) but can branch anywhere in virtual memory. Often there are 3 flavors of branch: short, medium and long. Some other assemblers would emit short and medium branches, unless told by this option to emit short and long branches.

``-t` (Temporary File Directory)`
  Some other assemblers may use a temporary file, and this option takes a filename being the directory to site the temporary file. Since `as` does not use a temporary disk file, this option makes no difference. ``-t'` needs exactly one filename.

The Vax version of the assembler accepts additional options when compiled for VMS:

``-h n'`
  External symbol or section (used for global variables) names are not case sensitive on VAX/VMS and always mapped to upper case. This is contrary to the C language definition which explicitly distinguishes upper and lower case. To implement a standard conforming C compiler, names must be changed (mapped) to preserve the case information. The default mapping is to convert all lower case characters to uppercase and adding an underscore followed by a 6 digit hex value, representing a 24 digit binary value. The one digits in the binary value represent which characters are uppercase in the original symbol name.

  The ``-h n'` option determines how we map names. This takes several values. No ``-h'` switch at all allows case hacking as described above. A value of zero (``-h0'`) implies names should be upper case, and inhibits the case hack. A value of 2 (``-h2'`) implies names should be all lower case, with no case hack. A value of 3 (``-h3'`) implies that case should be preserved. The value 1 is unused. The `-H` option directs `as` to display every mapped symbol during assembly.

  Symbols whose names include a dollar sign ``$'` are exceptions to the general name mapping. These symbols are normally only used to reference VMS library names. Such symbols are always mapped to upper case.

``-+'`
  The ``-+'` option causes `as` to truncate any symbol name larger than 31 characters. The ``-+'` option also prevents some code following the ``_main'` symbol normally added to make the object file compatible with Vax-11 "C".

``-1'`
  This option is ignored for backward compatibility with `as` version 1.x.

``-H'`
  The ``-H'` option causes `as` to print every symbol which was changed by case mapping.

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### 9.45.2 VAX Floating Point

Conversion of flonums to floating point is correct, and compatible with previous assemblers. Rounding is towards zero if the remainder is exactly half the least significant bit.

`D`, `F`, `G` and `H` floating point formats are understood.

Immediate floating literals (e.g. ``S`$6.9'`) are rendered correctly. Again, rounding is towards zero in the boundary case.

The `.float` directive produces `f` format numbers. The `.double` directive produces `d` format numbers.

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### 9.45.3 Vax Machine Directives

The Vax version of the assembler supports four directives for generating Vax floating point constants. They are described in the table below.

`.dfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `d` format 64-bit floating point constants.

`.ffloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `f` format 32-bit floating point constants.

`.gfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `g` format 64-bit floating point constants.

`.hfloat`
  This expects zero or more flonums, separated by commas, and assembles Vax `h` format 128-bit floating point constants.

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### 9.45.4 VAX Opcodes

All DEC mnemonics are supported. Beware that `case...` instructions have exactly 3 operands. The dispatch table that follows the `case...` instruction should be made with `.word` statements. This is compatible with all unix assemblers we know of.

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### 9.45.5 VAX Branch Improvement

Certain pseudo opcodes are permitted. They are for branch instructions. They expand to the shortest branch instruction that reaches the target. Generally these mnemonics are made by substituting ``j'` for ``b'` at the start of a DEC mnemonic. This feature is included both for compatibility and to help compilers. If you do not need this feature, avoid these opcodes. Here are the mnemonics, and the code they can expand into.

`jbsb`
  ``Jsb'` is already an instruction mnemonic, so we chose ``jbsb'`.
  (byte displacement)
    `bsbb ...`
  (word displacement)
    `bsbw ...`
  (long displacement)
    `jsb ...`
`jbr`
`jr`
  Unconditional branch.
  (byte displacement)
    `brb ...`
  (word displacement)
    `brw ...`
  (long displacement)
    `jmp ...`
`jCOND`
  COND may be any one of the conditional branches `neq`, `nequ`, `eql`, `eqlu`, `gtr`, `geq`, `lss`, `gtru`, `lequ`, `vc`, `vs`, `gequ`, `cc`, `lssu`, `cs`. COND may also be one of the bit tests `bs`, `bc`, `bss`, `bcs`, `bsc`, `bcc`, `bssi`, `bcci`, `lbs`, `lbc`. NOTCOND is the opposite condition to COND.
  (byte displacement)
    `bCOND ...`
  (word displacement)
    `bNOTCOND foo ; brw ... ; foo:`
  (long displacement)
    `bNOTCOND foo ; jmp ... ; foo:`
`jacbX`
  X may be one of `b d f g h l w`.
  (word displacement)
    `OPCODE ...`
  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp ... ;
        bar:

`jaobYYY`
  YYY may be one of `lss leq`.
`jsobZZZ`
  ZZZ may be one of `geq gtr`.
  (byte displacement)
    `OPCODE ...`
  (word displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: brw destination ;
        bar:

  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp destination ;
        bar:

`aobleq`
`aoblss`
`sobgeq`
`sobgtr`
  (byte displacement)
    `OPCODE ...`
  (word displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: brw destination ;
        bar:

  (long displacement)

        OPCODE ..., foo ;
        brb bar ;
        foo: jmp destination ;
        bar:

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### 9.45.6 VAX Operands

The immediate character is ``$'` for Unix compatibility, not ``#'` as DEC writes it.

The indirect character is ``*'` for Unix compatibility, not ``@'` as DEC writes it.

The displacement sizing character is ```'` (an accent grave) for Unix compatibility, not ``^'` as DEC writes it. The letter preceding ```'` may have either case. ``G'` is not understood, but all other letters (`b i l s w`) are understood.

Register names understood are `r0 r1 r2 ... r15 ap fp sp pc`. Upper and lower case letters are equivalent.

For instance

    tstb *w`$4(r5)

Any expression is permitted in an operand. Operands are comma separated.

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### 9.45.7 Not Supported on VAX

Vax bit fields can not be assembled with `as`. Someone can add the required code if they really need it.

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### 9.45.8 VAX Syntax

> 9.45.8.1 Special Characters |  |

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#### 9.45.8.1 Special Characters

The presence of a ``#'` appearing anywhere on a line indicates the start of a comment that extends to the end of that line.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

The ``;'` character can be used to separate statements on the same line.

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## 9.46 v850 Dependent Features

> 9.46.1 Options |  |
> 9.46.2 Syntax |  |
> 9.46.3 Floating Point |  |
> 9.46.4 V850 Machine Directives |  |
> 9.46.5 Opcodes |  |

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### 9.46.1 Options

`as` supports the following additional command-line options for the V850 processor family:

`-wsigned_overflow`
  Causes warnings to be produced when signed immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.

`-wunsigned_overflow`
  Causes warnings to be produced when unsigned immediate values overflow the space available for then within their opcodes. By default this option is disabled as it is possible to receive spurious warnings due to using exact bit patterns as immediate constants.

`-mv850`
  Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mv850e`
  Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mv850e1`
  Specifies that the assembled code should be marked as being targeted at the V850E1 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mv850any`
  Specifies that the assembled code should be marked as being targeted at the V850 processor but support instructions that are specific to the extended variants of the process. This allows the production of binaries that contain target specific code, but which are also intended to be used in a generic fashion. For example libgcc.a contains generic routines used by the code produced by GCC for all versions of the v850 architecture, together with support routines only used by the V850E architecture.

`-mv850e2`
  Specifies that the assembled code should be marked as being targeted at the V850E2 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mv850e2v3`
  Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mv850e2v4`
  This is an alias for ``-mv850e3v5'`.

`-mv850e3v5`
  Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`-mrelax`
  Enables relaxation. This allows the .longcall and .longjump pseudo ops to be used in the assembler source code. These ops label sections of code which are either a long function call or a long branch. The assembler will then flag these sections of code and the linker will attempt to relax them.

`-mgcc-abi`
  Marks the generated objecy file as supporting the old GCC ABI.

`-mrh850-abi`
  Marks the generated objecy file as supporting the RH850 ABI. This is the default.

`-m8byte-align`
  Marks the generated objecy file as supporting a maximum 64-bits of alignment for variables defined in the source code.

`-m4byte-align`
  Marks the generated objecy file as supporting a maximum 32-bits of alignment for variables defined in the source code. This is the default.

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### 9.46.2 Syntax

> 9.46.2.1 Special Characters |  |
> 9.46.2.2 Register Names |  |

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#### 9.46.2.1 Special Characters

``#'` is the line comment character. If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Two dashes (``--'`) can also be used to start a line comment.

The ``;'` character can be used to separate statements on the same line.

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#### 9.46.2.2 Register Names

`as` supports the following names for registers:

`general register 0`
  r0, zero
`general register 1`
  r1
`general register 2`
  r2, hp
`general register 3`
  r3, sp
`general register 4`
  r4, gp
`general register 5`
  r5, tp
`general register 6`
  r6
`general register 7`
  r7
`general register 8`
  r8
`general register 9`
  r9
`general register 10`
  r10
`general register 11`
  r11
`general register 12`
  r12
`general register 13`
  r13
`general register 14`
  r14
`general register 15`
  r15
`general register 16`
  r16
`general register 17`
  r17
`general register 18`
  r18
`general register 19`
  r19
`general register 20`
  r20
`general register 21`
  r21
`general register 22`
  r22
`general register 23`
  r23
`general register 24`
  r24
`general register 25`
  r25
`general register 26`
  r26
`general register 27`
  r27
`general register 28`
  r28
`general register 29`
  r29
`general register 30`
  r30, ep
`general register 31`
  r31, lp
`system register 0`
  eipc
`system register 1`
  eipsw
`system register 2`
  fepc
`system register 3`
  fepsw
`system register 4`
  ecr
`system register 5`
  psw
`system register 16`
  ctpc
`system register 17`
  ctpsw
`system register 18`
  dbpc
`system register 19`
  dbpsw
`system register 20`
  ctbp

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### 9.46.3 Floating Point

The V850 family uses IEEE floating-point numbers.

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### 9.46.4 V850 Machine Directives

`.offset <expression>`
  Moves the offset into the current section to the specified amount.

`.section "name", <type>`
  This is an extension to the standard .section directive. It sets the current section to be <type> and creates an alias for this section called "name".

`.v850`
  Specifies that the assembled code should be marked as being targeted at the V850 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e`
  Specifies that the assembled code should be marked as being targeted at the V850E processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e1`
  Specifies that the assembled code should be marked as being targeted at the V850E1 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e2`
  Specifies that the assembled code should be marked as being targeted at the V850E2 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e2v3`
  Specifies that the assembled code should be marked as being targeted at the V850E2V3 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e2v4`
  Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

`.v850e3v5`
  Specifies that the assembled code should be marked as being targeted at the V850E3V5 processor. This allows the linker to detect attempts to link such code with code assembled for other processors.

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### 9.46.5 Opcodes

`as` implements all the standard V850 opcodes.

`as` also implements the following pseudo ops:

`hi0()`
  Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

  ``mulhi hi0(here - there), r5, r6'`

  computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then multiplies it by the lower 16 bits in register 5, putting the result into register 6.

`lo()`
  Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

  ``addi lo(here - there), r5, r6'`

  computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 5, putting the result into register 6.

`hi()`
  Computes the higher 16 bits of the given expression and then adds the value of the most significant bit of the lower 16 bits of the expression and stores the result into the immediate operand field of the given instruction. For example the following code can be used to compute the address of the label 'here' and store it into register 6:

  ``movhi hi(here), r0, r6'` ``movea lo(here), r6, r6'`

  The reason for this special behaviour is that movea performs a sign extension on its immediate operand. So for example if the address of 'here' was 0xFFFFFFFF then without the special behaviour of the hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the movea instruction would takes its immediate operand, 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). With the hi() pseudo op adding in the top bit of the lo() pseudo op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - the right value.

`hilo()`
  Computes the 32 bit value of the given expression and stores it into the immediate operand field of the given instruction (which must be a mov instruction). For example:

  ``mov hilo(here), r6'`

  computes the absolute address of label 'here' and puts the result into register 6.

`sdaoff()`
  Computes the offset of the named variable from the start of the Small Data Area (whoes address is held in register 4, the GP register) and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example:

  ``ld.w sdaoff(_a_variable)[gp],r6'`

  loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +/- 32K of the address held in the GP register. [Note the linker assumes that the GP register contains a fixed address set to the address of the label called '__gp'. This can either be set up automatically by the linker, or specifically set by using the ``--defsym __gp=<value>'` command line option].

`tdaoff()`
  Computes the offset of the named variable from the start of the Tiny Data Area (whoes address is held in register 30, the EP register) and stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate operand field of the given instruction. For example:

  ``sld.w tdaoff(_a_variable)[ep],r6'`

  loads the contents of the location pointed to by the label '_a_variable' into register 6, provided that the label is located somewhere within +256 bytes of the address held in the EP register. [Note the linker assumes that the EP register contains a fixed address set to the address of the label called '__ep'. This can either be set up automatically by the linker, or specifically set by using the ``--defsym __ep=<value>'` command line option].

`zdaoff()`
  Computes the offset of the named variable from address 0 and stores the result as a 16 bit signed value in the immediate operand field of the given instruction. For example:

  ``movea zdaoff(_a_variable),zero,r6'`

  puts the address of the label '_a_variable' into register 6, assuming that the label is somewhere within the first 32K of memory. (Strictly speaking it also possible to access the last 32K of memory as well, as the offsets are signed).

`ctoff()`
  Computes the offset of the named variable from the start of the Call Table Area (whoes address is helg in system register 20, the CTBP register) and stores the result a 6 or 16 bit unsigned value in the immediate field of then given instruction or piece of data. For example:

  ``callt ctoff(table_func1)'`

  will put the call the function whoes address is held in the call table at the location labeled 'table_func1'.

`.longcall `name``
  Indicates that the following sequence of instructions is a long call to function `name`. The linker will attempt to shorten this call sequence if `name` is within a 22bit offset of the call. Only valid if the `-mrelax` command line switch has been enabled.

`.longjump `name``
  Indicates that the following sequence of instructions is a long jump to label `name`. The linker will attempt to shorten this code sequence if `name` is within a 22bit offset of the jump. Only valid if the `-mrelax` command line switch has been enabled.

For information on the V850 instruction set, see V850 Family 32-/16-Bit single-Chip Microcontroller Architecture Manual from NEC. Ltd.

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## 9.47 XStormy16 Dependent Features

> 9.47.1 Syntax |  |
> 9.47.2 XStormy16 Machine Directives |  | Machine Directives
> 9.47.3 XStormy16 Pseudo-Opcodes |  | Pseudo-Opcodes

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### 9.47.1 Syntax

> 9.47.1.1 Special Characters |  |

[ < ] | [ > ] |  | [ << ] | [ Up ] | [ >> ] |  |  |  |  | [Top] | [Contents] | [Index] | [ ? ]

#### 9.47.1.1 Special Characters

``#'` is the line comment character. If a ``#'` appears as the first character of a line, the whole line is treated as a comment, but in this case the line can also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

A semicolon (``;'`) can be used to start a comment that extends from wherever the character appears on the line up to the end of the line.

The ``|'` character can be used to separate statements on the same line.

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### 9.47.2 XStormy16 Machine Directives

`.16bit_pointers`
  Like the ``--16bit-pointers'` command line option this directive indicates that the assembly code makes use of 16-bit pointers.

`.32bit_pointers`
  Like the ``--32bit-pointers'` command line option this directive indicates that the assembly code makes use of 32-bit pointers.

`.no_pointers`
  Like the ``--no-pointers'` command line option this directive indicates that the assembly code does not makes use pointers.

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### 9.47.3 XStormy16 Pseudo-Opcodes

`as` implements all the standard XStormy16 opcodes.

`as` also implements the following pseudo ops:

`@lo()`
  Computes the lower 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

  ``add r6, @lo(here - there)'`

  computes the difference between the address of labels 'here' and 'there', takes the lower 16 bits of this difference and adds it to register 6.

`@hi()`
  Computes the higher 16 bits of the given expression and stores it into the immediate operand field of the given instruction. For example:

  ``addc r7, @hi(here - there)'`

  computes the difference between the address of labels 'here' and 'there', takes the upper 16 bits of this difference, shifts it down 16 bits and then adds it, along with the carry bit, to the value in register 7.

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## 9.48 Xtensa Dependent Features

This chapter covers features of the GNU assembler that are specific to the Xtensa architecture. For details about the Xtensa instruction set, please consult the Xtensa Instruction Set Architecture (ISA) Reference Manual.

> 9.48.1 Command Line Options |  | Command-line Options.
> 9.48.2 Assembler Syntax |  | Assembler Syntax for Xtensa Processors.
> 9.48.3 Xtensa Optimizations |  | Assembler Optimizations.
> 9.48.4 Xtensa Relaxation |  | Other Automatic Transformations.
> 9.48.5 Directives |  | Directives for Xtensa Processors.

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### 9.48.1 Command Line Options

`--text-section-literals | --no-text-section-literals`
  Control the treatment of literal pools. The default is ``--no-text-section-literals'`, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With ``--text-section-literals'`, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the `L32R` instructions in the text section. These options only affect literals referenced via PC-relative `L32R` instructions; literals for absolute mode `L32R` instructions are handled separately. See section literal.

`--absolute-literals | --no-absolute-literals`
  Indicate to the assembler whether `L32R` instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute `L32R` relocations. Otherwise, only the PC-relative `L32R` relocations can be used.

`--target-align | --no-target-align`
  Enable or disable automatic alignment to reduce branch penalties at some expense in code size. See section Automatic Instruction Alignment. This optimization is enabled by default. Note that the assembler will always align instructions like `LOOP` that have fixed alignment requirements.

`--longcalls | --no-longcalls`
  Enable or disable transformation of call instructions to allow calls across a greater range of addresses. See section Function Call Relaxation. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is ``--no-longcalls'`.

`--transform | --no-transform`
  Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is ``--transform'`; ``--no-transform'` should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using ``--no-transform'` causes out of range instruction operands to be errors.

`--rename-section oldname=newname`
  Rename the oldname section to newname. This option can be used multiple times to rename multiple sections.

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### 9.48.2 Assembler Syntax

Block comments are delimited by ``/*'` and ``*/'`. End of line comments may be introduced with either ``#'` or ``//'`.

If a ``#'` appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see section 3.3 Comments) or a preprocessor control command (see section 3.1 Preprocessing).

Instructions consist of a leading opcode or macro name followed by whitespace and an optional comma-separated list of operands:

    opcode [operand, ...]

Instructions must be separated by a newline or semicolon (``;'`).

FLIX instructions, which bundle multiple opcodes together in a single instruction, are specified by enclosing the bundled opcodes inside braces:

    {
    [format]
    opcode0 [operands]
    opcode1 [operands]
    opcode2 [operands]
    ...
    }

The opcodes in a FLIX instruction are listed in the same order as the corresponding instruction slots in the TIE format declaration. Directives and labels are not allowed inside the braces of a FLIX instruction. A particular TIE format name can optionally be specified immediately after the opening brace, but this is usually unnecessary. The assembler will automatically search for a format that can encode the specified opcodes, so the format name need only be specified in rare cases where there is more than one applicable format and where it matters which of those formats is used. A FLIX instruction can also be specified on a single line by separating the opcodes with semicolons:

    { [format;] opcode0 [operands]; opcode1 [operands]; opcode2 [operands]; ... }

If an opcode can only be encoded in a FLIX instruction but is not specified as part of a FLIX bundle, the assembler will choose the smallest format where the opcode can be encoded and will fill unused instruction slots with no-ops.

> 9.48.2.1 Opcode Names |  | Opcode Naming Conventions.
> 9.48.2.2 Register Names |  | Register Naming.

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#### 9.48.2.1 Opcode Names

See the Xtensa Instruction Set Architecture (ISA) Reference Manual for a complete list of opcodes and descriptions of their semantics.

If an opcode name is prefixed with an underscore character (``_'`), `as` will not transform that instruction in any way. The underscore prefix disables both optimization (see section Xtensa Optimizations) and relaxation (see section Xtensa Relaxation) for that particular instruction. Only use the underscore prefix when it is essential to select the exact opcode produced by the assembler. Using this feature unnecessarily makes the code less efficient by disabling assembler optimization and less flexible by disabling relaxation.

Note that this special handling of underscore prefixes only applies to Xtensa opcodes, not to either built-in macros or user-defined macros. When an underscore prefix is used with a macro (e.g., `_MOV`), it refers to a different macro. The assembler generally provides built-in macros both with and without the underscore prefix, where the underscore versions behave as if the underscore carries through to the instructions in the macros. For example, `_MOV` may expand to `_MOV.N`.

The underscore prefix only applies to individual instructions, not to series of instructions. For example, if a series of instructions have underscore prefixes, the assembler will not transform the individual instructions, but it may insert other instructions between them (e.g., to align a `LOOP` instruction). To prevent the assembler from modifying a series of instructions as a whole, use the `no-transform` directive. See section transform.

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#### 9.48.2.2 Register Names

The assembly syntax for a register file entry is the "short" name for a TIE register file followed by the index into that register file. For example, the general-purpose `AR` register file has a short name of `a`, so these registers are named `a0`...`a15`. As a special feature, `sp` is also supported as a synonym for `a1`. Additional registers may be added by processor configuration options and by designer-defined TIE extensions. An initial ``$'` character is optional in all register names.

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### 9.48.3 Xtensa Optimizations

The optimizations currently supported by `as` are generation of density instructions where appropriate and automatic branch target alignment.

> 9.48.3.1 Using Density Instructions |  |
> 9.48.3.2 Automatic Instruction Alignment |  |

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#### 9.48.3.1 Using Density Instructions

The Xtensa instruction set has a code density option that provides 16-bit versions of some of the most commonly used opcodes. Use of these opcodes can significantly reduce code size. When possible, the assembler automatically translates instructions from the core Xtensa instruction set into equivalent instructions from the Xtensa code density option. This translation can be disabled by using underscore prefixes (see section Opcode Names), by using the ``--no-transform'` command-line option (see section Command Line Options), or by using the `no-transform` directive (see section transform).

It is a good idea not to use the density instructions directly. The assembler will automatically select dense instructions where possible. If you later need to use an Xtensa processor without the code density option, the same assembly code will then work without modification.

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#### 9.48.3.2 Automatic Instruction Alignment

The Xtensa assembler will automatically align certain instructions, both to optimize performance and to satisfy architectural requirements.

As an optimization to improve performance, the assembler attempts to align branch targets so they do not cross instruction fetch boundaries. (Xtensa processors can be configured with either 32-bit or 64-bit instruction fetch widths.) An instruction immediately following a call is treated as a branch target in this context, because it will be the target of a return from the call. This alignment has the potential to reduce branch penalties at some expense in code size. This optimization is enabled by default. You can disable it with the ``--no-target-align'` command-line option (see section Command Line Options).

The target alignment optimization is done without adding instructions that could increase the execution time of the program. If there are density instructions in the code preceding a target, the assembler can change the target alignment by widening some of those instructions to the equivalent 24-bit instructions. Extra bytes of padding can be inserted immediately following unconditional jump and return instructions. This approach is usually successful in aligning many, but not all, branch targets.

The `LOOP` family of instructions must be aligned such that the first instruction in the loop body does not cross an instruction fetch boundary (e.g., with a 32-bit fetch width, a `LOOP` instruction must be on either a 1 or 2 mod 4 byte boundary). The assembler knows about this restriction and inserts the minimal number of 2 or 3 byte no-op instructions to satisfy it. When no-op instructions are added, any label immediately preceding the original loop will be moved in order to refer to the loop instruction, not the newly generated no-op instruction. To preserve binary compatibility across processors with different fetch widths, the assembler conservatively assumes a 32-bit fetch width when aligning `LOOP` instructions (except if the first instruction in the loop is a 64-bit instruction).

Previous versions of the assembler automatically aligned `ENTRY` instructions to 4-byte boundaries, but that alignment is now the programmer's responsibility.

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### 9.48.4 Xtensa Relaxation

When an instruction operand is outside the range allowed for that particular instruction field, `as` can transform the code to use a functionally-equivalent instruction or sequence of instructions. This process is known as relaxation. This is typically done for branch instructions because the distance of the branch targets is not known until assembly-time. The Xtensa assembler offers branch relaxation and also extends this concept to function calls, `MOVI` instructions and other instructions with immediate fields.

> 9.48.4.1 Conditional Branch Relaxation |  | Relaxation of Branches.
> 9.48.4.2 Function Call Relaxation |  | Relaxation of Function Calls.
> 9.48.4.3 Other Immediate Field Relaxation |  | Relaxation of other Immediate Fields.

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#### 9.48.4.1 Conditional Branch Relaxation

When the target of a branch is too far away from the branch itself, i.e., when the offset from the branch to the target is too large to fit in the immediate field of the branch instruction, it may be necessary to replace the branch with a branch around a jump. For example,

        beqz    a2, L

may result in:

        bnez.n  a2, M
        j L
    M:

(The `BNEZ.N` instruction would be used in this example only if the density option is available. Otherwise, `BNEZ` would be used.)

This relaxation works well because the unconditional jump instruction has a much larger offset range than the various conditional branches. However, an error will occur if a branch target is beyond the range of a jump instruction. `as` cannot relax unconditional jumps. Similarly, an error will occur if the original input contains an unconditional jump to a target that is out of range.

Branch relaxation is enabled by default. It can be disabled by using underscore prefixes (see section Opcode Names), the ``--no-transform'` command-line option (see section Command Line Options), or the `no-transform` directive (see section transform).

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#### 9.48.4.2 Function Call Relaxation

Function calls may require relaxation because the Xtensa immediate call instructions (`CALL0`, `CALL4`, `CALL8` and `CALL12`) provide a PC-relative offset of only 512 Kbytes in either direction. For larger programs, it may be necessary to use indirect calls (`CALLX0`, `CALLX4`, `CALLX8` and `CALLX12`) where the target address is specified in a register. The Xtensa assembler can automatically relax immediate call instructions into indirect call instructions. This relaxation is done by loading the address of the called function into the callee's return address register and then using a `CALLX` instruction. So, for example:

        call8 func

might be relaxed to:

        .literal .L1, func
        l32r    a8, .L1
        callx8  a8

Because the addresses of targets of function calls are not generally known until link-time, the assembler must assume the worst and relax all the calls to functions in other source files, not just those that really will be out of range. The linker can recognize calls that were unnecessarily relaxed, and it will remove the overhead introduced by the assembler for those cases where direct calls are sufficient.

Call relaxation is disabled by default because it can have a negative effect on both code size and performance, although the linker can usually eliminate the unnecessary overhead. If a program is too large and some of the calls are out of range, function call relaxation can be enabled using the ``--longcalls'` command-line option or the `longcalls` directive (see section longcalls).

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#### 9.48.4.3 Other Immediate Field Relaxation

The assembler normally performs the following other relaxations. They can be disabled by using underscore prefixes (see section Opcode Names), the ``--no-transform'` command-line option (see section Command Line Options), or the `no-transform` directive (see section transform).

The `MOVI` machine instruction can only materialize values in the range from -2048 to 2047. Values outside this range are best materialized with `L32R` instructions. Thus:

        movi a0, 100000

is assembled into the following machine code:

        .literal .L1, 100000
        l32r a0, .L1

The `L8UI` machine instruction can only be used with immediate offsets in the range from 0 to 255. The `L16SI` and `L16UI` machine instructions can only be used with offsets from 0 to 510. The `L32I` machine instruction can only be used with offsets from 0 to 1020. A load offset outside these ranges can be materialized with an `L32R` instruction if the destination register of the load is different than the source address register. For example:

        l32i a1, a0, 2040

is translated to:

        .literal .L1, 2040
        l32r a1, .L1
        add a1, a0, a1
        l32i a1, a1, 0

If the load destination and source address register are the same, an out-of-range offset causes an error.

The Xtensa `ADDI` instruction only allows immediate operands in the range from -128 to 127. There are a number of alternate instruction sequences for the `ADDI` operation. First, if the immediate is 0, the `ADDI` will be turned into a `MOV.N` instruction (or the equivalent `OR` instruction if the code density option is not available). If the `ADDI` immediate is outside of the range -128 to 127, but inside the range -32896 to 32639, an `ADDMI` instruction or `ADDMI`/`ADDI` sequence will be used. Finally, if the immediate is outside of this range and a free register is available, an `L32R`/`ADD` sequence will be used with a literal allocated from the literal pool.

For example:

        addi    a5, a6, 0
        addi    a5, a6, 512
        addi    a5, a6, 513
        addi    a5, a6, 50000

is assembled into the following:

        .literal .L1, 50000
        mov.n   a5, a6
        addmi   a5, a6, 0x200
        addmi   a5, a6, 0x200
        addi    a5, a5, 1
        l32r    a5, .L1
        add     a5, a6, a5

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### 9.48.5 Directives

The Xtensa assembler supports a region-based directive syntax:

        .begin directive [options]
        ...
        .end directive

All the Xtensa-specific directives that apply to a region of code use this syntax.

The directive applies to code between the `.begin` and the `.end`. The state of the option after the `.end` reverts to what it was before the `.begin`. A nested `.begin`/`.end` region can further change the state of the directive without having to be aware of its outer state. For example, consider:

        .begin no-transform
    L:  add a0, a1, a2
        .begin transform
    M:  add a0, a1, a2
        .end transform
    N:  add a0, a1, a2
        .end no-transform

The `ADD` opcodes at `L` and `N` in the outer `no-transform` region both result in `ADD` machine instructions, but the assembler selects an `ADD.N` instruction for the `ADD` at `M` in the inner `transform` region.

The advantage of this style is that it works well inside macros which can preserve the context of their callers.

The following directives are available:

> 9.48.5.1 schedule |  | Enable instruction scheduling.
> 9.48.5.2 longcalls |  | Use Indirect Calls for Greater Range.
> 9.48.5.3 transform |  | Disable All Assembler Transformations.
> 9.48.5.4 literal |  | Intermix Literals with Instructions.
> 9.48.5.5 literal_position |  | Specify Inline Literal Pool Locations.
> 9.48.5.6 literal_prefix |  | Specify Literal Section Name Prefix.
> 9.48.5.7 absolute-literals |  | Control PC-Relative vs. Absolute Literals.

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#### 9.48.5.1 schedule

The `schedule` directive is recognized only for compatibility with Tensilica's assembler.

        .begin [no-]schedule
        .end [no-]schedule

This directive is ignored and has no effect on `as`.

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#### 9.48.5.2 longcalls

The `longcalls` directive enables or disables function call relaxation. See section Function Call Relaxation.

        .begin [no-]longcalls
        .end [no-]longcalls

Call relaxation is disabled by default unless the ``--longcalls'` command-line option is specified. The `longcalls` directive overrides the default determined by the command-line options.

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#### 9.48.5.3 transform

This directive enables or disables all assembler transformation, including relaxation (see section Xtensa Relaxation) and optimization (see section Xtensa Optimizations).

        .begin [no-]transform
        .end [no-]transform

Transformations are enabled by default unless the ``--no-transform'` option is used. The `transform` directive overrides the default determined by the command-line options. An underscore opcode prefix, disabling transformation of that opcode, always takes precedence over both directives and command-line flags.

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#### 9.48.5.4 literal

The `.literal` directive is used to define literal pool data, i.e., read-only 32-bit data accessed via `L32R` instructions.

        .literal label, value[, value...]

This directive is similar to the standard `.word` directive, except that the actual location of the literal data is determined by the assembler and linker, not by the position of the `.literal` directive. Using this directive gives the assembler freedom to locate the literal data in the most appropriate place and possibly to combine identical literals. For example, the code:

        entry sp, 40
        .literal .L1, sym
        l32r    a4, .L1

can be used to load a pointer to the symbol `sym` into register `a4`. The value of `sym` will not be placed between the `ENTRY` and `L32R` instructions; instead, the assembler puts the data in a literal pool.

Literal pools are placed by default in separate literal sections; however, when using the ``--text-section-literals'` option (see section Command Line Options), the literal pools for PC-relative mode `L32R` instructions are placed in the current section.(3) These text section literal pools are created automatically before `ENTRY` instructions and manually after ``.literal_position'` directives (see section literal_position). If there are no preceding `ENTRY` instructions, explicit `.literal_position` directives must be used to place the text section literal pools; otherwise, `as` will report an error.

When literals are placed in separate sections, the literal section names are derived from the names of the sections where the literals are defined. The base literal section names are `.literal` for PC-relative mode `L32R` instructions and `.lit4` for absolute mode `L32R` instructions (see section absolute-literals). These base names are used for literals defined in the default `.text` section. For literals defined in other sections or within the scope of a `literal_prefix` directive (see section literal_prefix), the following rules determine the literal section name:

1. If the current section is a member of a section group, the literal section name includes the group name as a suffix to the base `.literal` or `.lit4` name, with a period to separate the base name and group name. The literal section is also made a member of the group.

2. If the current section name (or `literal_prefix` value) begins with "`.gnu.linkonce.kind.`", the literal section name is formed by replacing "`.kind`" with the base `.literal` or `.lit4` name. For example, for literals defined in a section named `.gnu.linkonce.t.func`, the literal section will be `.gnu.linkonce.literal.func` or `.gnu.linkonce.lit4.func`.

3. If the current section name (or `literal_prefix` value) ends with `.text`, the literal section name is formed by replacing that suffix with the base `.literal` or `.lit4` name. For example, for literals defined in a section named `.iram0.text`, the literal section will be `.iram0.literal` or `.iram0.lit4`.

4. If none of the preceding conditions apply, the literal section name is formed by adding the base `.literal` or `.lit4` name as a suffix to the current section name (or `literal_prefix` value).

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#### 9.48.5.5 literal_position

When using ``--text-section-literals'` to place literals inline in the section being assembled, the `.literal_position` directive can be used to mark a potential location for a literal pool.

        .literal_position

The `.literal_position` directive is ignored when the ``--text-section-literals'` option is not used or when `L32R` instructions use the absolute addressing mode.

The assembler will automatically place text section literal pools before `ENTRY` instructions, so the `.literal_position` directive is only needed to specify some other location for a literal pool. You may need to add an explicit jump instruction to skip over an inline literal pool.

For example, an interrupt vector does not begin with an `ENTRY` instruction so the assembler will be unable to automatically find a good place to put a literal pool. Moreover, the code for the interrupt vector must be at a specific starting address, so the literal pool cannot come before the start of the code. The literal pool for the vector must be explicitly positioned in the middle of the vector (before any uses of the literals, due to the negative offsets used by PC-relative `L32R` instructions). The `.literal_position` directive can be used to do this. In the following code, the literal for ``M'` will automatically be aligned correctly and is placed after the unconditional jump.

        .global M
    code_start:
        j continue
        .literal_position
        .align 4
    continue:
        movi    a4, M

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#### 9.48.5.6 literal_prefix

The `literal_prefix` directive allows you to override the default literal section names, which are derived from the names of the sections where the literals are defined.

        .begin literal_prefix [name]
        .end literal_prefix

For literals defined within the delimited region, the literal section names are derived from the name argument instead of the name of the current section. The rules used to derive the literal section names do not change. See section literal. If the name argument is omitted, the literal sections revert to the defaults. This directive has no effect when using the ``--text-section-literals'` option (see section Command Line Options).

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#### 9.48.5.7 absolute-literals

The `absolute-literals` and `no-absolute-literals` directives control the absolute vs. PC-relative mode for `L32R` instructions. These are relevant only for Xtensa configurations that include the absolute addressing option for `L32R` instructions.

        .begin [no-]absolute-literals
        .end [no-]absolute-literals

These directives do not change the `L32R` mode--they only cause the assembler to emit the appropriate kind of relocation for `L32R` instructions and to place the literal values in the appropriate section. To change the `L32R` mode, the program must write the `LITBASE` special register. It is the programmer's responsibility to keep track of the mode and indicate to the assembler which mode is used in each region of code.

If the Xtensa configuration includes the absolute `L32R` addressing option, the default is to assume absolute `L32R` addressing unless the ``--no-absolute-literals'` command-line option is specified. Otherwise, the default is to assume PC-relative `L32R` addressing. The `absolute-literals` directive can then be used to override the default determined by the command-line options.

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