Intel® Threading Building Blocks. logic_sim sample

# Intel® Threading Building Blocks.
Logic_sim sample

This directory contains a simple tbb::flow example that performs simplistic digital logic simulations with basic logic gates that can be easily composed to create more interesting circuits. It exemplifies the multifunction_node and the indexer_node CPF, among others.

System Requirements

For the most up to date system requirements, see the release notes.

Files

basics.h
  Several I/O devices and basic gates.
one_bit_adder.h
  A one-bit full adder composed of basic gates.
four_bit_adder.h
  A four-bit full adder composed of one-bit adders.
D_latch.h
  A D-latch composed of basic gates.
test_all.cpp
  A simple test program that exercises the code in the headers.
Makefile
  Makefile for building the example.

Directories

msvs
  Contains Microsoft* Visual Studio* workspace for building and running the example with the Intel® C++ Compiler (Windows* systems only).

For information about the minimum supported version of IDE, see release notes.

Build instructions

General build directions can be found here.

Usage

`test_all -h`
  Prints the help for command line options
`test_all [#threads=value] [verbose] [silent] [#threads]`
  `#threads` is the number of threads to use; a range of the form `low[:high]` where `low` and optional `high` are non-negative integers, or `'auto'` for a platform-specific default number.
  `verbose` print diagnostic output to screen
  `silent` limits output to timing info; overrides verbose
To run a short version of this example, e.g., for use with Intel® Parallel Inspector:
  Build a debug version of the example (see the build instructions).
  Run it with the desired number of threads, e.g., `test_all 4`.

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