Machine (P#0 total=516423680KB PlatformName=pSeries PlatformModel="CHRP IBM,9179-MHB" Backend=Linux Architecture=ppc)
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      Package L#0 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#0 (size=4096KB linesize=128)
          L2Cache L#0 (size=256KB linesize=128 ways=8)
            L1dCache L#0 (size=32KB linesize=128 ways=8)
              L1iCache L#0 (size=32KB linesize=128 ways=4)
                Core L#0 (P#0)
                  PU L#0 (P#0)
                  PU L#1 (P#1)
                  PU L#2 (P#2)
                  PU L#3 (P#3)
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        L3Cache L#1 (size=4096KB linesize=128)
          L2Cache L#1 (size=256KB linesize=128 ways=8)
            L1dCache L#1 (size=32KB linesize=128 ways=8)
              L1iCache L#1 (size=32KB linesize=128 ways=4)
                Core L#1 (P#4)
                  PU L#4 (P#4)
                  PU L#5 (P#5)
                  PU L#6 (P#6)
                  PU L#7 (P#7)
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        L3Cache L#2 (size=4096KB linesize=128)
          L2Cache L#2 (size=256KB linesize=128 ways=8)
            L1dCache L#2 (size=32KB linesize=128 ways=8)
              L1iCache L#2 (size=32KB linesize=128 ways=4)
                Core L#2 (P#8)
                  PU L#8 (P#8)
                  PU L#9 (P#9)
                  PU L#10 (P#10)
                  PU L#11 (P#11)
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        L3Cache L#3 (size=4096KB linesize=128)
          L2Cache L#3 (size=256KB linesize=128 ways=8)
            L1dCache L#3 (size=32KB linesize=128 ways=8)
              L1iCache L#3 (size=32KB linesize=128 ways=4)
                Core L#3 (P#12)
                  PU L#12 (P#12)
                  PU L#13 (P#13)
                  PU L#14 (P#14)
                  PU L#15 (P#15)
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        L3Cache L#4 (size=4096KB linesize=128)
          L2Cache L#4 (size=256KB linesize=128 ways=8)
            L1dCache L#4 (size=32KB linesize=128 ways=8)
              L1iCache L#4 (size=32KB linesize=128 ways=4)
                Core L#4 (P#16)
                  PU L#16 (P#16)
                  PU L#17 (P#17)
                  PU L#18 (P#18)
                  PU L#19 (P#19)
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        L3Cache L#5 (size=4096KB linesize=128)
          L2Cache L#5 (size=256KB linesize=128 ways=8)
            L1dCache L#5 (size=32KB linesize=128 ways=8)
              L1iCache L#5 (size=32KB linesize=128 ways=4)
                Core L#5 (P#20)
                  PU L#20 (P#20)
                  PU L#21 (P#21)
                  PU L#22 (P#22)
                  PU L#23 (P#23)
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        L3Cache L#6 (size=4096KB linesize=128)
          L2Cache L#6 (size=256KB linesize=128 ways=8)
            L1dCache L#6 (size=32KB linesize=128 ways=8)
              L1iCache L#6 (size=32KB linesize=128 ways=4)
                Core L#6 (P#24)
                  PU L#24 (P#24)
                  PU L#25 (P#25)
                  PU L#26 (P#26)
                  PU L#27 (P#27)
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        L3Cache L#7 (size=4096KB linesize=128)
          L2Cache L#7 (size=256KB linesize=128 ways=8)
            L1dCache L#7 (size=32KB linesize=128 ways=8)
              L1iCache L#7 (size=32KB linesize=128 ways=4)
                Core L#7 (P#28)
                  PU L#28 (P#28)
                  PU L#29 (P#29)
                  PU L#30 (P#30)
                  PU L#31 (P#31)
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      Package L#8 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#8 (size=4096KB linesize=128)
          L2Cache L#8 (size=256KB linesize=128 ways=8)
            L1dCache L#8 (size=32KB linesize=128 ways=8)
              L1iCache L#8 (size=32KB linesize=128 ways=4)
                Core L#8 (P#32)
                  PU L#32 (P#32)
                  PU L#33 (P#33)
                  PU L#34 (P#34)
                  PU L#35 (P#35)
      Package L#9 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#9 (size=4096KB linesize=128)
          L2Cache L#9 (size=256KB linesize=128 ways=8)
            L1dCache L#9 (size=32KB linesize=128 ways=8)
              L1iCache L#9 (size=32KB linesize=128 ways=4)
                Core L#9 (P#36)
                  PU L#36 (P#36)
                  PU L#37 (P#37)
                  PU L#38 (P#38)
                  PU L#39 (P#39)
      Package L#10 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#10 (size=4096KB linesize=128)
          L2Cache L#10 (size=256KB linesize=128 ways=8)
            L1dCache L#10 (size=32KB linesize=128 ways=8)
              L1iCache L#10 (size=32KB linesize=128 ways=4)
                Core L#10 (P#40)
                  PU L#40 (P#40)
                  PU L#41 (P#41)
                  PU L#42 (P#42)
                  PU L#43 (P#43)
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        L3Cache L#11 (size=4096KB linesize=128)
          L2Cache L#11 (size=256KB linesize=128 ways=8)
            L1dCache L#11 (size=32KB linesize=128 ways=8)
              L1iCache L#11 (size=32KB linesize=128 ways=4)
                Core L#11 (P#44)
                  PU L#44 (P#44)
                  PU L#45 (P#45)
                  PU L#46 (P#46)
                  PU L#47 (P#47)
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        L3Cache L#12 (size=4096KB linesize=128)
          L2Cache L#12 (size=256KB linesize=128 ways=8)
            L1dCache L#12 (size=32KB linesize=128 ways=8)
              L1iCache L#12 (size=32KB linesize=128 ways=4)
                Core L#12 (P#48)
                  PU L#48 (P#48)
                  PU L#49 (P#49)
                  PU L#50 (P#50)
                  PU L#51 (P#51)
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        L3Cache L#13 (size=4096KB linesize=128)
          L2Cache L#13 (size=256KB linesize=128 ways=8)
            L1dCache L#13 (size=32KB linesize=128 ways=8)
              L1iCache L#13 (size=32KB linesize=128 ways=4)
                Core L#13 (P#52)
                  PU L#52 (P#52)
                  PU L#53 (P#53)
                  PU L#54 (P#54)
                  PU L#55 (P#55)
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        L3Cache L#14 (size=4096KB linesize=128)
          L2Cache L#14 (size=256KB linesize=128 ways=8)
            L1dCache L#14 (size=32KB linesize=128 ways=8)
              L1iCache L#14 (size=32KB linesize=128 ways=4)
                Core L#14 (P#56)
                  PU L#56 (P#56)
                  PU L#57 (P#57)
                  PU L#58 (P#58)
                  PU L#59 (P#59)
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        L3Cache L#15 (size=4096KB linesize=128)
          L2Cache L#15 (size=256KB linesize=128 ways=8)
            L1dCache L#15 (size=32KB linesize=128 ways=8)
              L1iCache L#15 (size=32KB linesize=128 ways=4)
                Core L#15 (P#60)
                  PU L#60 (P#60)
                  PU L#61 (P#61)
                  PU L#62 (P#62)
                  PU L#63 (P#63)
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        L3Cache L#16 (size=4096KB linesize=128)
          L2Cache L#16 (size=256KB linesize=128 ways=8)
            L1dCache L#16 (size=32KB linesize=128 ways=8)
              L1iCache L#16 (size=32KB linesize=128 ways=4)
                Core L#16 (P#64)
                  PU L#64 (P#64)
                  PU L#65 (P#65)
                  PU L#66 (P#66)
                  PU L#67 (P#67)
      Package L#17 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#17 (size=4096KB linesize=128)
          L2Cache L#17 (size=256KB linesize=128 ways=8)
            L1dCache L#17 (size=32KB linesize=128 ways=8)
              L1iCache L#17 (size=32KB linesize=128 ways=4)
                Core L#17 (P#68)
                  PU L#68 (P#68)
                  PU L#69 (P#69)
                  PU L#70 (P#70)
                  PU L#71 (P#71)
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        L3Cache L#18 (size=4096KB linesize=128)
          L2Cache L#18 (size=256KB linesize=128 ways=8)
            L1dCache L#18 (size=32KB linesize=128 ways=8)
              L1iCache L#18 (size=32KB linesize=128 ways=4)
                Core L#18 (P#72)
                  PU L#72 (P#72)
                  PU L#73 (P#73)
                  PU L#74 (P#74)
                  PU L#75 (P#75)
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        L3Cache L#19 (size=4096KB linesize=128)
          L2Cache L#19 (size=256KB linesize=128 ways=8)
            L1dCache L#19 (size=32KB linesize=128 ways=8)
              L1iCache L#19 (size=32KB linesize=128 ways=4)
                Core L#19 (P#76)
                  PU L#76 (P#76)
                  PU L#77 (P#77)
                  PU L#78 (P#78)
                  PU L#79 (P#79)
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        L3Cache L#20 (size=4096KB linesize=128)
          L2Cache L#20 (size=256KB linesize=128 ways=8)
            L1dCache L#20 (size=32KB linesize=128 ways=8)
              L1iCache L#20 (size=32KB linesize=128 ways=4)
                Core L#20 (P#80)
                  PU L#80 (P#80)
                  PU L#81 (P#81)
                  PU L#82 (P#82)
                  PU L#83 (P#83)
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        L3Cache L#21 (size=4096KB linesize=128)
          L2Cache L#21 (size=256KB linesize=128 ways=8)
            L1dCache L#21 (size=32KB linesize=128 ways=8)
              L1iCache L#21 (size=32KB linesize=128 ways=4)
                Core L#21 (P#84)
                  PU L#84 (P#84)
                  PU L#85 (P#85)
                  PU L#86 (P#86)
                  PU L#87 (P#87)
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        L3Cache L#22 (size=4096KB linesize=128)
          L2Cache L#22 (size=256KB linesize=128 ways=8)
            L1dCache L#22 (size=32KB linesize=128 ways=8)
              L1iCache L#22 (size=32KB linesize=128 ways=4)
                Core L#22 (P#88)
                  PU L#88 (P#88)
                  PU L#89 (P#89)
                  PU L#90 (P#90)
                  PU L#91 (P#91)
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        L3Cache L#23 (size=4096KB linesize=128)
          L2Cache L#23 (size=256KB linesize=128 ways=8)
            L1dCache L#23 (size=32KB linesize=128 ways=8)
              L1iCache L#23 (size=32KB linesize=128 ways=4)
                Core L#23 (P#92)
                  PU L#92 (P#92)
                  PU L#93 (P#93)
                  PU L#94 (P#94)
                  PU L#95 (P#95)
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      Package L#24 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#24 (size=4096KB linesize=128)
          L2Cache L#24 (size=256KB linesize=128 ways=8)
            L1dCache L#24 (size=32KB linesize=128 ways=8)
              L1iCache L#24 (size=32KB linesize=128 ways=4)
                Core L#24 (P#96)
                  PU L#96 (P#96)
                  PU L#97 (P#97)
                  PU L#98 (P#98)
                  PU L#99 (P#99)
      Package L#25 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#25 (size=4096KB linesize=128)
          L2Cache L#25 (size=256KB linesize=128 ways=8)
            L1dCache L#25 (size=32KB linesize=128 ways=8)
              L1iCache L#25 (size=32KB linesize=128 ways=4)
                Core L#25 (P#100)
                  PU L#100 (P#100)
                  PU L#101 (P#101)
                  PU L#102 (P#102)
                  PU L#103 (P#103)
      Package L#26 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#26 (size=4096KB linesize=128)
          L2Cache L#26 (size=256KB linesize=128 ways=8)
            L1dCache L#26 (size=32KB linesize=128 ways=8)
              L1iCache L#26 (size=32KB linesize=128 ways=4)
                Core L#26 (P#104)
                  PU L#104 (P#104)
                  PU L#105 (P#105)
                  PU L#106 (P#106)
                  PU L#107 (P#107)
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        L3Cache L#27 (size=4096KB linesize=128)
          L2Cache L#27 (size=256KB linesize=128 ways=8)
            L1dCache L#27 (size=32KB linesize=128 ways=8)
              L1iCache L#27 (size=32KB linesize=128 ways=4)
                Core L#27 (P#108)
                  PU L#108 (P#108)
                  PU L#109 (P#109)
                  PU L#110 (P#110)
                  PU L#111 (P#111)
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        L3Cache L#28 (size=4096KB linesize=128)
          L2Cache L#28 (size=256KB linesize=128 ways=8)
            L1dCache L#28 (size=32KB linesize=128 ways=8)
              L1iCache L#28 (size=32KB linesize=128 ways=4)
                Core L#28 (P#112)
                  PU L#112 (P#112)
                  PU L#113 (P#113)
                  PU L#114 (P#114)
                  PU L#115 (P#115)
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          L2Cache L#29 (size=256KB linesize=128 ways=8)
            L1dCache L#29 (size=32KB linesize=128 ways=8)
              L1iCache L#29 (size=32KB linesize=128 ways=4)
                Core L#29 (P#116)
                  PU L#116 (P#116)
                  PU L#117 (P#117)
                  PU L#118 (P#118)
                  PU L#119 (P#119)
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        L3Cache L#30 (size=4096KB linesize=128)
          L2Cache L#30 (size=256KB linesize=128 ways=8)
            L1dCache L#30 (size=32KB linesize=128 ways=8)
              L1iCache L#30 (size=32KB linesize=128 ways=4)
                Core L#30 (P#120)
                  PU L#120 (P#120)
                  PU L#121 (P#121)
                  PU L#122 (P#122)
                  PU L#123 (P#123)
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        L3Cache L#31 (size=4096KB linesize=128)
          L2Cache L#31 (size=256KB linesize=128 ways=8)
            L1dCache L#31 (size=32KB linesize=128 ways=8)
              L1iCache L#31 (size=32KB linesize=128 ways=4)
                Core L#31 (P#124)
                  PU L#124 (P#124)
                  PU L#125 (P#125)
                  PU L#126 (P#126)
                  PU L#127 (P#127)
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        L3Cache L#32 (size=4096KB linesize=128)
          L2Cache L#32 (size=256KB linesize=128 ways=8)
            L1dCache L#32 (size=32KB linesize=128 ways=8)
              L1iCache L#32 (size=32KB linesize=128 ways=4)
                Core L#32 (P#128)
                  PU L#128 (P#128)
                  PU L#129 (P#129)
                  PU L#130 (P#130)
                  PU L#131 (P#131)
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        L3Cache L#33 (size=4096KB linesize=128)
          L2Cache L#33 (size=256KB linesize=128 ways=8)
            L1dCache L#33 (size=32KB linesize=128 ways=8)
              L1iCache L#33 (size=32KB linesize=128 ways=4)
                Core L#33 (P#132)
                  PU L#132 (P#132)
                  PU L#133 (P#133)
                  PU L#134 (P#134)
                  PU L#135 (P#135)
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        L3Cache L#34 (size=4096KB linesize=128)
          L2Cache L#34 (size=256KB linesize=128 ways=8)
            L1dCache L#34 (size=32KB linesize=128 ways=8)
              L1iCache L#34 (size=32KB linesize=128 ways=4)
                Core L#34 (P#136)
                  PU L#136 (P#136)
                  PU L#137 (P#137)
                  PU L#138 (P#138)
                  PU L#139 (P#139)
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        L3Cache L#35 (size=4096KB linesize=128)
          L2Cache L#35 (size=256KB linesize=128 ways=8)
            L1dCache L#35 (size=32KB linesize=128 ways=8)
              L1iCache L#35 (size=32KB linesize=128 ways=4)
                Core L#35 (P#140)
                  PU L#140 (P#140)
                  PU L#141 (P#141)
                  PU L#142 (P#142)
                  PU L#143 (P#143)
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        L3Cache L#36 (size=4096KB linesize=128)
          L2Cache L#36 (size=256KB linesize=128 ways=8)
            L1dCache L#36 (size=32KB linesize=128 ways=8)
              L1iCache L#36 (size=32KB linesize=128 ways=4)
                Core L#36 (P#144)
                  PU L#144 (P#144)
                  PU L#145 (P#145)
                  PU L#146 (P#146)
                  PU L#147 (P#147)
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          L2Cache L#37 (size=256KB linesize=128 ways=8)
            L1dCache L#37 (size=32KB linesize=128 ways=8)
              L1iCache L#37 (size=32KB linesize=128 ways=4)
                Core L#37 (P#148)
                  PU L#148 (P#148)
                  PU L#149 (P#149)
                  PU L#150 (P#150)
                  PU L#151 (P#151)
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        L3Cache L#38 (size=4096KB linesize=128)
          L2Cache L#38 (size=256KB linesize=128 ways=8)
            L1dCache L#38 (size=32KB linesize=128 ways=8)
              L1iCache L#38 (size=32KB linesize=128 ways=4)
                Core L#38 (P#152)
                  PU L#152 (P#152)
                  PU L#153 (P#153)
                  PU L#154 (P#154)
                  PU L#155 (P#155)
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        L3Cache L#39 (size=4096KB linesize=128)
          L2Cache L#39 (size=256KB linesize=128 ways=8)
            L1dCache L#39 (size=32KB linesize=128 ways=8)
              L1iCache L#39 (size=32KB linesize=128 ways=4)
                Core L#39 (P#156)
                  PU L#156 (P#156)
                  PU L#157 (P#157)
                  PU L#158 (P#158)
                  PU L#159 (P#159)
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      Package L#40 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#40 (size=4096KB linesize=128)
          L2Cache L#40 (size=256KB linesize=128 ways=8)
            L1dCache L#40 (size=32KB linesize=128 ways=8)
              L1iCache L#40 (size=32KB linesize=128 ways=4)
                Core L#40 (P#160)
                  PU L#160 (P#160)
                  PU L#161 (P#161)
                  PU L#162 (P#162)
                  PU L#163 (P#163)
      Package L#41 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#41 (size=4096KB linesize=128)
          L2Cache L#41 (size=256KB linesize=128 ways=8)
            L1dCache L#41 (size=32KB linesize=128 ways=8)
              L1iCache L#41 (size=32KB linesize=128 ways=4)
                Core L#41 (P#164)
                  PU L#164 (P#164)
                  PU L#165 (P#165)
                  PU L#166 (P#166)
                  PU L#167 (P#167)
      Package L#42 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#42 (size=4096KB linesize=128)
          L2Cache L#42 (size=256KB linesize=128 ways=8)
            L1dCache L#42 (size=32KB linesize=128 ways=8)
              L1iCache L#42 (size=32KB linesize=128 ways=4)
                Core L#42 (P#168)
                  PU L#168 (P#168)
                  PU L#169 (P#169)
                  PU L#170 (P#170)
                  PU L#171 (P#171)
      Package L#43 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#43 (size=4096KB linesize=128)
          L2Cache L#43 (size=256KB linesize=128 ways=8)
            L1dCache L#43 (size=32KB linesize=128 ways=8)
              L1iCache L#43 (size=32KB linesize=128 ways=4)
                Core L#43 (P#172)
                  PU L#172 (P#172)
                  PU L#173 (P#173)
                  PU L#174 (P#174)
                  PU L#175 (P#175)
      Package L#44 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#44 (size=4096KB linesize=128)
          L2Cache L#44 (size=256KB linesize=128 ways=8)
            L1dCache L#44 (size=32KB linesize=128 ways=8)
              L1iCache L#44 (size=32KB linesize=128 ways=4)
                Core L#44 (P#176)
                  PU L#176 (P#176)
                  PU L#177 (P#177)
                  PU L#178 (P#178)
                  PU L#179 (P#179)
      Package L#45 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#45 (size=4096KB linesize=128)
          L2Cache L#45 (size=256KB linesize=128 ways=8)
            L1dCache L#45 (size=32KB linesize=128 ways=8)
              L1iCache L#45 (size=32KB linesize=128 ways=4)
                Core L#45 (P#180)
                  PU L#180 (P#180)
                  PU L#181 (P#181)
                  PU L#182 (P#182)
                  PU L#183 (P#183)
      Package L#46 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#46 (size=4096KB linesize=128)
          L2Cache L#46 (size=256KB linesize=128 ways=8)
            L1dCache L#46 (size=32KB linesize=128 ways=8)
              L1iCache L#46 (size=32KB linesize=128 ways=4)
                Core L#46 (P#184)
                  PU L#184 (P#184)
                  PU L#185 (P#185)
                  PU L#186 (P#186)
                  PU L#187 (P#187)
      Package L#47 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#47 (size=4096KB linesize=128)
          L2Cache L#47 (size=256KB linesize=128 ways=8)
            L1dCache L#47 (size=32KB linesize=128 ways=8)
              L1iCache L#47 (size=32KB linesize=128 ways=4)
                Core L#47 (P#188)
                  PU L#188 (P#188)
                  PU L#189 (P#189)
                  PU L#190 (P#190)
                  PU L#191 (P#191)
  Group0 L#3 (total=123731968KB)
    Group1 L#6 (total=66846720KB)
      NUMANode L#6 (P#12 local=66846720KB total=66846720KB)
      Package L#48 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#48 (size=4096KB linesize=128)
          L2Cache L#48 (size=256KB linesize=128 ways=8)
            L1dCache L#48 (size=32KB linesize=128 ways=8)
              L1iCache L#48 (size=32KB linesize=128 ways=4)
                Core L#48 (P#192)
                  PU L#192 (P#192)
                  PU L#193 (P#193)
                  PU L#194 (P#194)
                  PU L#195 (P#195)
      Package L#49 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#49 (size=4096KB linesize=128)
          L2Cache L#49 (size=256KB linesize=128 ways=8)
            L1dCache L#49 (size=32KB linesize=128 ways=8)
              L1iCache L#49 (size=32KB linesize=128 ways=4)
                Core L#49 (P#196)
                  PU L#196 (P#196)
                  PU L#197 (P#197)
                  PU L#198 (P#198)
                  PU L#199 (P#199)
      Package L#50 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#50 (size=4096KB linesize=128)
          L2Cache L#50 (size=256KB linesize=128 ways=8)
            L1dCache L#50 (size=32KB linesize=128 ways=8)
              L1iCache L#50 (size=32KB linesize=128 ways=4)
                Core L#50 (P#200)
                  PU L#200 (P#200)
                  PU L#201 (P#201)
                  PU L#202 (P#202)
                  PU L#203 (P#203)
      Package L#51 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#51 (size=4096KB linesize=128)
          L2Cache L#51 (size=256KB linesize=128 ways=8)
            L1dCache L#51 (size=32KB linesize=128 ways=8)
              L1iCache L#51 (size=32KB linesize=128 ways=4)
                Core L#51 (P#204)
                  PU L#204 (P#204)
                  PU L#205 (P#205)
                  PU L#206 (P#206)
                  PU L#207 (P#207)
      Package L#52 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#52 (size=4096KB linesize=128)
          L2Cache L#52 (size=256KB linesize=128 ways=8)
            L1dCache L#52 (size=32KB linesize=128 ways=8)
              L1iCache L#52 (size=32KB linesize=128 ways=4)
                Core L#52 (P#208)
                  PU L#208 (P#208)
                  PU L#209 (P#209)
                  PU L#210 (P#210)
                  PU L#211 (P#211)
      Package L#53 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#53 (size=4096KB linesize=128)
          L2Cache L#53 (size=256KB linesize=128 ways=8)
            L1dCache L#53 (size=32KB linesize=128 ways=8)
              L1iCache L#53 (size=32KB linesize=128 ways=4)
                Core L#53 (P#212)
                  PU L#212 (P#212)
                  PU L#213 (P#213)
                  PU L#214 (P#214)
                  PU L#215 (P#215)
      Package L#54 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#54 (size=4096KB linesize=128)
          L2Cache L#54 (size=256KB linesize=128 ways=8)
            L1dCache L#54 (size=32KB linesize=128 ways=8)
              L1iCache L#54 (size=32KB linesize=128 ways=4)
                Core L#54 (P#216)
                  PU L#216 (P#216)
                  PU L#217 (P#217)
                  PU L#218 (P#218)
                  PU L#219 (P#219)
      Package L#55 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#55 (size=4096KB linesize=128)
          L2Cache L#55 (size=256KB linesize=128 ways=8)
            L1dCache L#55 (size=32KB linesize=128 ways=8)
              L1iCache L#55 (size=32KB linesize=128 ways=4)
                Core L#55 (P#220)
                  PU L#220 (P#220)
                  PU L#221 (P#221)
                  PU L#222 (P#222)
                  PU L#223 (P#223)
    Group1 L#7 (total=56885248KB)
      NUMANode L#7 (P#13 local=56885248KB total=56885248KB)
      Package L#56 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#56 (size=4096KB linesize=128)
          L2Cache L#56 (size=256KB linesize=128 ways=8)
            L1dCache L#56 (size=32KB linesize=128 ways=8)
              L1iCache L#56 (size=32KB linesize=128 ways=4)
                Core L#56 (P#224)
                  PU L#224 (P#224)
                  PU L#225 (P#225)
                  PU L#226 (P#226)
                  PU L#227 (P#227)
      Package L#57 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#57 (size=4096KB linesize=128)
          L2Cache L#57 (size=256KB linesize=128 ways=8)
            L1dCache L#57 (size=32KB linesize=128 ways=8)
              L1iCache L#57 (size=32KB linesize=128 ways=4)
                Core L#57 (P#228)
                  PU L#228 (P#228)
                  PU L#229 (P#229)
                  PU L#230 (P#230)
                  PU L#231 (P#231)
      Package L#58 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#58 (size=4096KB linesize=128)
          L2Cache L#58 (size=256KB linesize=128 ways=8)
            L1dCache L#58 (size=32KB linesize=128 ways=8)
              L1iCache L#58 (size=32KB linesize=128 ways=4)
                Core L#58 (P#232)
                  PU L#232 (P#232)
                  PU L#233 (P#233)
                  PU L#234 (P#234)
                  PU L#235 (P#235)
      Package L#59 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#59 (size=4096KB linesize=128)
          L2Cache L#59 (size=256KB linesize=128 ways=8)
            L1dCache L#59 (size=32KB linesize=128 ways=8)
              L1iCache L#59 (size=32KB linesize=128 ways=4)
                Core L#59 (P#236)
                  PU L#236 (P#236)
                  PU L#237 (P#237)
                  PU L#238 (P#238)
                  PU L#239 (P#239)
      Package L#60 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#60 (size=4096KB linesize=128)
          L2Cache L#60 (size=256KB linesize=128 ways=8)
            L1dCache L#60 (size=32KB linesize=128 ways=8)
              L1iCache L#60 (size=32KB linesize=128 ways=4)
                Core L#60 (P#240)
                  PU L#240 (P#240)
                  PU L#241 (P#241)
                  PU L#242 (P#242)
                  PU L#243 (P#243)
      Package L#61 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#61 (size=4096KB linesize=128)
          L2Cache L#61 (size=256KB linesize=128 ways=8)
            L1dCache L#61 (size=32KB linesize=128 ways=8)
              L1iCache L#61 (size=32KB linesize=128 ways=4)
                Core L#61 (P#244)
                  PU L#244 (P#244)
                  PU L#245 (P#245)
                  PU L#246 (P#246)
                  PU L#247 (P#247)
      Package L#62 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#62 (size=4096KB linesize=128)
          L2Cache L#62 (size=256KB linesize=128 ways=8)
            L1dCache L#62 (size=32KB linesize=128 ways=8)
              L1iCache L#62 (size=32KB linesize=128 ways=4)
                Core L#62 (P#248)
                  PU L#248 (P#248)
                  PU L#249 (P#249)
                  PU L#250 (P#250)
                  PU L#251 (P#251)
      Package L#63 (CPUModel="POWER7 (architected), altivec supported" CPURevision="2.1 (pvr 003f 0201)")
        L3Cache L#63 (size=4096KB linesize=128)
          L2Cache L#63 (size=256KB linesize=128 ways=8)
            L1dCache L#63 (size=32KB linesize=128 ways=8)
              L1iCache L#63 (size=32KB linesize=128 ways=4)
                Core L#63 (P#252)
                  PU L#252 (P#252)
                  PU L#253 (P#253)
                  PU L#254 (P#254)
                  PU L#255 (P#255)
depth 0:             1 Machine (type #0)
 depth 1:            4 Group0 (type #12)
  depth 2:           8 Group1 (type #12)
   depth 3:          64 Package (type #1)
    depth 4:         64 L3Cache (type #6)
     depth 5:        64 L2Cache (type #5)
      depth 6:       64 L1dCache (type #4)
       depth 7:      64 L1iCache (type #9)
        depth 8:     64 Core (type #2)
         depth 9:    256 PU (type #3)
Special depth -3:    8 NUMANode (type #13)
Relative latency matrix (name NUMALatency kind 5) between 8 NUMANodes (depth -3) by logical indexes:
 index     0     1     2     3     4     5     6     7
     0    10    20    40    40    40    40    40    40
     1    20    10    40    40    40    40    40    40
     2    40    40    10    20    40    40    40    40
     3    40    40    20    10    40    40    40    40
     4    40    40    40    40    10    20    40    40
     5    40    40    40    40    20    10    40    40
     6    40    40    40    40    40    40    10    20
     7    40    40    40    40    40    40    20    10
Topology not from this system
