source_filename = "test"
target datalayout = "e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"

define i32 @function_0() local_unnamed_addr {
dec_label_pc_0:
  %edi.global-to-local = alloca i32, align 4
  %edx.global-to-local = alloca i32, align 4
  %esi.global-to-local = alloca i32, align 4
  %fpsw.global-to-local = alloca i32, align 4
  %fpu_stat_TOP.global-to-local = alloca i3, align 1
  %st6.global-to-local = alloca x86_fp80, align 4
  %st7.global-to-local = alloca x86_fp80, align 4
  %tmp254 = call double @__decompiler_undefined_function_3()
  %stack_var_-50 = alloca double, align 8
  %v0_3 = load i32, i32* %esi.global-to-local, align 4
  %v1_3 = add i32 %v0_3, -120
  %v2_3 = inttoptr i32 %v1_3 to i128*
  %v3_3 = load i128, i128* %v2_3, align 4
  %v4_3 = call i128 @__asm_movupd(i128 %v3_3)
  %v1_8 = add i32 %v0_3, -104
  %v2_8 = inttoptr i32 %v1_8 to i64*
  %v3_8 = load i64, i64* %v2_8, align 4
  %v4_8 = call i128 @__asm_movsd(i64 %v3_8)
  %v1_d = load i32, i32* %edi.global-to-local, align 4
  %v2_d = add i32 %v1_d, -32
  %v3_d = inttoptr i32 %v2_d to i128*
  %v4_d = load i128, i128* %v3_d, align 4
  %v5_d = call i128 @__asm_mulpd(i128 %v4_3, i128 %v4_d)
  %v2_12 = add i32 %v1_d, -32
  %v3_12 = inttoptr i32 %v2_12 to i64*
  %v4_12 = load i64, i64* %v3_12, align 4
  %v5_12 = call i128 @__asm_mulsd(i128 %v4_8, i64 %v4_12)
  %v1_17 = load i32, i32* %edi.global-to-local, align 4
  %v2_17 = add i32 %v1_17, -64
  %v3_17 = inttoptr i32 %v2_17 to i128*
  %v4_17 = load i128, i128* %v3_17, align 4
  %v5_17 = call i128 @__asm_addpd(i128 %v5_d, i128 %v4_17)
  %v2_1c = add i32 %v1_17, -48
  %v3_1c = inttoptr i32 %v2_1c to i64*
  %v4_1c = load i64, i64* %v3_1c, align 4
  %v5_1c = call i128 @__asm_addsd(i128 %v5_12, i64 %v4_1c)
  %v0_21 = load i32, i32* %edi.global-to-local, align 4
  %v1_21 = add i32 %v0_21, -76
  %v2_21 = inttoptr i32 %v1_21 to i32*
  %v3_21 = load i32, i32* %v2_21, align 4
  %v10_21 = icmp eq i32 %v3_21, 0
  br i1 %v10_21, label %dec_label_pc_40, label %dec_label_pc_27

dec_label_pc_27:                                  ; preds = %dec_label_pc_0
  %v0_27 = load i32, i32* %esi.global-to-local, align 4
  %v1_27 = add i32 %v0_27, 112
  %v2_27 = inttoptr i32 %v1_27 to i64*
  %v3_27 = load i64, i64* %v2_27, align 4
  %v4_27 = call i128 @__asm_movsd(i64 %v3_27)
  %v1_2c = load i32, i32* %edi.global-to-local, align 4
  %v2_2c = add i32 %v1_2c, -32
  %v3_2c = inttoptr i32 %v2_2c to i64*
  %v4_2c = load i64, i64* %v3_2c, align 4
  %v5_2c = call i128 @__asm_mulsd(i128 %v4_27, i64 %v4_2c)
  %v0_31 = load i32, i32* %esi.global-to-local, align 4
  %v1_31 = add i32 %v0_31, -120
  %v2_31 = inttoptr i32 %v1_31 to i128*
  %v3_31 = load i128, i128* %v2_31, align 4
  call void @__asm_movupd.1(i128 %v3_31, i128 %v5_17)
  %v1_36 = call i32 @__asm_movsd.2(i128 %v5_1c)
  %v3_36 = add i32 %v0_31, -104
  %v4_36 = sext i32 %v1_36 to i64
  %v5_36 = inttoptr i32 %v3_36 to i64*
  store i64 %v4_36, i64* %v5_36, align 4
  %v1_3b = call i32 @__asm_movsd.2(i128 %v5_2c)
  %v2_3b = load i32, i32* %esi.global-to-local, align 4
  %v3_3b = add i32 %v2_3b, 112
  %v4_3b = sext i32 %v1_3b to i64
  %v5_3b = inttoptr i32 %v3_3b to i64*
  store i64 %v4_3b, i64* %v5_3b, align 4
  br label %dec_label_pc_40

dec_label_pc_40:                                  ; preds = %dec_label_pc_27, %dec_label_pc_0
  %v2_40 = load double, double* %stack_var_-50, align 8
  %v3_40 = fptrunc double %v2_40 to float
  %v4_40 = bitcast float %v3_40 to i32
  %v5_40 = sext i32 %v4_40 to i128
  call void @__asm_movupd.1(i128 %v5_40, i128 %v5_17)
  %v1_45 = call i32 @__asm_movsd.2(i128 %v5_1c)
  %v4_45 = sext i32 %v1_45 to i64
  %v6_45 = bitcast i64 %v4_45 to double
  %v0_4b = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v5_4b = fpext double %tmp254 to x86_fp80
  store x86_fp80 %v5_4b, x86_fp80* %st7.global-to-local, align 4
  %v3_4f = load double, double* %stack_var_-50, align 8
  %v8_4f = fpext double %v3_4f to x86_fp80
  %v9_4f = add i3 %v0_4b, -2
  store i3 %v9_4f, i3* %fpu_stat_TOP.global-to-local, align 1
  store x86_fp80 %v8_4f, x86_fp80* %st6.global-to-local, align 4
  %v3_52 = call i32 @__asm_fpatan(i32 %v1_45)
  %v3_58 = fmul x86_fp80 %v5_4b, %v5_4b
  %v3_5a = load double, double* %stack_var_-50, align 8
  %v8_5a = fpext double %v3_5a to x86_fp80
  %v3_5d = fmul x86_fp80 %v8_5a, %v8_5a
  %v4_5f = fadd x86_fp80 %v3_58, %v3_5d
  %v2_61 = call x86_fp80 @llvm.sqrt.f80(x86_fp80 %v4_5f)
  %tmp261 = fptrunc x86_fp80 %v2_61 to double
  store double %tmp261, double* %stack_var_-50, align 8
  %v1_66 = load x86_fp80, x86_fp80* %st6.global-to-local, align 4
  %v6_66 = add i3 %v0_4b, -1
  %v1_6a = load i32, i32* %edi.global-to-local, align 4
  %v2_6a = add i32 %v1_6a, 16
  %v3_6a = inttoptr i32 %v2_6a to double*
  %v4_6a = load double, double* %v3_6a, align 4
  %v5_6a = fpext double %v4_6a to x86_fp80
  store x86_fp80 %v5_6a, x86_fp80* %st6.global-to-local, align 4
  %v2_6d = load i32, i32* %esi.global-to-local, align 4
  %v3_6d = add i32 %v2_6d, -32
  %v5_6d = inttoptr i32 %v3_6d to double*
  store double %v4_6a, double* %v5_6d, align 4
  store i3 %v6_66, i3* %fpu_stat_TOP.global-to-local, align 1
  %v1_70 = add i32 %v1_6a, -100
  %v2_70 = inttoptr i32 %v1_70 to i32*
  %v3_70 = load i32, i32* %v2_70, align 4
  store i32 %v3_70, i32* %edx.global-to-local, align 4
  %v8_a1 = fpext double %v6_45 to x86_fp80
  br label %dec_label_pc_73

dec_label_pc_73:                                  ; preds = %dec_label_pc_bf.dec_label_pc_73_crit_edge, %dec_label_pc_40
  %v2_a5 = phi i32 [ %v1_6a, %dec_label_pc_40 ], [ %v2_77.pre, %dec_label_pc_bf.dec_label_pc_73_crit_edge ]
  %v0_73 = phi i3 [ %v6_66, %dec_label_pc_40 ], [ %storemerge, %dec_label_pc_bf.dec_label_pc_73_crit_edge ]
  %stack_var_-42.0.in = phi x86_fp80 [ %v1_66, %dec_label_pc_40 ], [ %v7_77, %dec_label_pc_bf.dec_label_pc_73_crit_edge ]
  %v6_73 = add i3 %v0_73, -1
  store x86_fp80 %stack_var_-42.0.in, x86_fp80* %st6.global-to-local, align 4
  %v3_77 = add i32 %v2_a5, 8
  %v4_77 = inttoptr i32 %v3_77 to double*
  %v5_77 = load double, double* %v4_77, align 4
  %v6_77 = fpext double %v5_77 to x86_fp80
  %v7_77 = fadd x86_fp80 %stack_var_-42.0.in, %v6_77
  store x86_fp80 %v7_77, x86_fp80* %st6.global-to-local, align 4
  %v3_7e = add i32 %v2_a5, -80
  %v4_7e = inttoptr i32 %v3_7e to i32*
  %v5_7e = load i32, i32* %v4_7e, align 4
  %v6_7e = sitofp i32 %v5_7e to x86_fp80
  %v7_7e = fdiv x86_fp80 %v7_77, %v6_7e
  store x86_fp80 %v7_7e, x86_fp80* %st6.global-to-local, align 4
  %v3_85 = add i32 %v2_a5, -84
  %v4_85 = inttoptr i32 %v3_85 to i32*
  %v5_85 = load i32, i32* %v4_85, align 4
  %v6_85 = sitofp i32 %v5_85 to x86_fp80
  %v7_85 = fmul x86_fp80 %v7_7e, %v6_85
  %v2_88 = call x86_fp80 @llvm.fabs.f80(x86_fp80 %v7_85)
  %v3_88 = fcmp olt x86_fp80 %v2_88, 0xK403E8000000000000000
  %v4_88 = call x86_fp80 @llvm.cos.f80(x86_fp80 %v7_85)
  %storemerge9 = select i1 %v3_88, x86_fp80 %v4_88, x86_fp80 %v7_85
  store x86_fp80 %storemerge9, x86_fp80* %st6.global-to-local, align 4
  %v1_8a = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v3_8a = add i32 %v2_a5, -96
  %v4_8a = inttoptr i32 %v3_8a to double*
  %v5_8a = load double, double* %v4_8a, align 4
  %v6_8a = fpext double %v5_8a to x86_fp80
  %v7_8a = fmul x86_fp80 %v1_8a, %v6_8a
  %v4_8d = load double, double* %stack_var_-50, align 8
  %v9_8d = fpext double %v4_8d to x86_fp80
  %v10_8d = fadd x86_fp80 %v7_8a, %v9_8d
  store x86_fp80 %v10_8d, x86_fp80* %st7.global-to-local, align 4
  %v3_90 = add i32 %v2_a5, -16
  %v4_90 = inttoptr i32 %v3_90 to double*
  %v5_90 = load double, double* %v4_90, align 4
  %v6_90 = fpext double %v5_90 to x86_fp80
  %v7_90 = fsub x86_fp80 %v10_8d, %v6_90
  %v3_93 = fmul x86_fp80 %v7_90, %v7_90
  store x86_fp80 %v3_93, x86_fp80* %st7.global-to-local, align 4
  store x86_fp80 %v7_7e, x86_fp80* %st6.global-to-local, align 4
  %v3_99 = add i32 %v2_a5, -88
  %v4_99 = inttoptr i32 %v3_99 to i32*
  %v5_99 = load i32, i32* %v4_99, align 4
  %v6_99 = sitofp i32 %v5_99 to x86_fp80
  %v7_99 = fmul x86_fp80 %v7_7e, %v6_99
  %v2_9c = call x86_fp80 @llvm.fabs.f80(x86_fp80 %v7_99)
  %v3_9c = fcmp olt x86_fp80 %v2_9c, 0xK403E8000000000000000
  %v4_9c = call x86_fp80 @llvm.sin.f80(x86_fp80 %v7_99)
  %storemerge8 = select i1 %v3_9c, x86_fp80 %v4_9c, x86_fp80 %v7_99
  store x86_fp80 %storemerge8, x86_fp80* %st6.global-to-local, align 4
  %v5_9e = load double, double* %v4_8a, align 4
  %v6_9e = fpext double %v5_9e to x86_fp80
  %v7_9e = fmul x86_fp80 %storemerge8, %v6_9e
  %v9_a1 = fadd x86_fp80 %v7_9e, %v8_a1
  store x86_fp80 %v9_a1, x86_fp80* %st6.global-to-local, align 4
  %v5_a5 = load double, double* %v4_90, align 4
  %v6_a5 = fpext double %v5_a5 to x86_fp80
  %v7_a5 = fsub x86_fp80 %v9_a1, %v6_a5
  %v3_a8 = fmul x86_fp80 %v7_a5, %v7_a5
  store x86_fp80 %v3_a8, x86_fp80* %st6.global-to-local, align 4
  %v4_aa = fadd x86_fp80 %v3_93, %v3_a8
  store i3 %v6_73, i3* %fpu_stat_TOP.global-to-local, align 1
  %v2_ac = call x86_fp80 @llvm.sqrt.f80(x86_fp80 %v4_aa)
  store x86_fp80 %v2_ac, x86_fp80* %st7.global-to-local, align 4
  %v2_b1 = call i32 @__asm_wait(x86_fp80 %v7_77)
  %v0_b2 = load i32, i32* %fpsw.global-to-local, align 4
  %v1_b2 = call i16 @__asm_fnstsw(i32 %v0_b2)
  %v2_b2 = sext i16 %v1_b2 to i32
  %v4_b2 = and i32 %v2_b1, -65536
  %tmp263 = udiv i32 %v2_b2, 2
  %v12_b4 = and i32 %tmp263, 32512
  %v2_b2.masked = and i32 %v2_b2, -65281
  %v13_b4 = or i32 %v4_b2, %v2_b2.masked
  %v14_b4 = or i32 %v13_b4, %v12_b4
  %v15_b47 = and i32 %v2_b2, 256
  %v16_b4 = icmp ne i32 %v15_b47, 0
  %v1_b6 = icmp eq i1 %v16_b4, false
  %v0_bd = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  br i1 %v1_b6, label %dec_label_pc_bf, label %dec_label_pc_b8

dec_label_pc_b8:                                  ; preds = %dec_label_pc_73
  %v1_bd = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v2_b8 = load i32, i32* %esi.global-to-local, align 4
  %v3_b8 = add i32 %v2_b8, -32
  %v4_b8 = fptrunc x86_fp80 %v1_bd to double
  %v5_b8 = inttoptr i32 %v3_b8 to double*
  store double %v4_b8, double* %v5_b8, align 4
  br label %dec_label_pc_bf

dec_label_pc_bf:                                  ; preds = %dec_label_pc_73, %dec_label_pc_b8
  %storemerge = add i3 %v0_bd, 1
  store i3 %storemerge, i3* %fpu_stat_TOP.global-to-local, align 1
  %v0_bf = load i32, i32* %edx.global-to-local, align 4
  %v1_bf = add i32 %v0_bf, -1
  store i32 %v1_bf, i32* %edx.global-to-local, align 4
  %v8_c0 = icmp sgt i32 %v0_bf, 1
  br i1 %v8_c0, label %dec_label_pc_bf.dec_label_pc_73_crit_edge, label %dec_label_pc_c2

dec_label_pc_bf.dec_label_pc_73_crit_edge:        ; preds = %dec_label_pc_bf
  %v2_77.pre = load i32, i32* %edi.global-to-local, align 4
  br label %dec_label_pc_73

dec_label_pc_c2:                                  ; preds = %dec_label_pc_bf
  %v1_c2 = load i32, i32* %esi.global-to-local, align 4
  %v2_c2 = add i32 %v1_c2, -32
  %v3_c2 = inttoptr i32 %v2_c2 to double*
  %v4_c2 = load double, double* %v3_c2, align 4
  %v5_c2 = fpext double %v4_c2 to x86_fp80
  store i3 %v0_bd, i3* %fpu_stat_TOP.global-to-local, align 1
  store x86_fp80 %v5_c2, x86_fp80* %st7.global-to-local, align 4
  %v2_c5 = load i32, i32* %edi.global-to-local, align 4
  %v3_c5 = add i32 %v2_c5, -72
  %v4_c5 = inttoptr i32 %v3_c5 to double*
  %v5_c5 = load double, double* %v4_c5, align 4
  %v6_c5 = fpext double %v5_c5 to x86_fp80
  %v7_c5 = fsub x86_fp80 %v5_c2, %v6_c5
  store x86_fp80 %v7_c5, x86_fp80* %st7.global-to-local, align 4
  %v1_c8 = add i32 %v2_c5, -76
  %v2_c8 = inttoptr i32 %v1_c8 to i32*
  %v3_c8 = load i32, i32* %v2_c8, align 4
  %v10_c8 = icmp eq i32 %v3_c8, 0
  %v1_cc = icmp eq i1 %v10_c8, false
  br i1 %v1_cc, label %dec_label_pc_d1, label %dec_label_pc_ce

dec_label_pc_ce:                                  ; preds = %dec_label_pc_c2
  %v3_ce = add i32 %v2_c5, -32
  %v4_ce = inttoptr i32 %v3_ce to double*
  %v5_ce = load double, double* %v4_ce, align 4
  %v6_ce = fpext double %v5_ce to x86_fp80
  %v7_ce = fdiv x86_fp80 %v7_c5, %v6_ce
  store x86_fp80 %v7_ce, x86_fp80* %st7.global-to-local, align 4
  br label %dec_label_pc_d1

dec_label_pc_d1:                                  ; preds = %dec_label_pc_ce, %dec_label_pc_c2
  %v1_d1 = phi x86_fp80 [ %v7_ce, %dec_label_pc_ce ], [ %v7_c5, %dec_label_pc_c2 ]
  %v4_d1 = fptrunc x86_fp80 %v1_d1 to double
  store double %v4_d1, double* %v3_c2, align 4
  store i3 %storemerge, i3* %fpu_stat_TOP.global-to-local, align 1
  ret i32 %v14_b4
}

declare i128 @__asm_movupd(i128) local_unnamed_addr

declare i128 @__asm_movsd(i64) local_unnamed_addr

declare i128 @__asm_mulpd(i128, i128) local_unnamed_addr

declare i128 @__asm_mulsd(i128, i64) local_unnamed_addr

declare i128 @__asm_addpd(i128, i128) local_unnamed_addr

declare i128 @__asm_addsd(i128, i64) local_unnamed_addr

declare void @__asm_movupd.1(i128, i128) local_unnamed_addr

declare i32 @__asm_movsd.2(i128) local_unnamed_addr

declare i32 @__asm_fpatan(i32) local_unnamed_addr

; Function Attrs: nounwind readnone speculatable
declare x86_fp80 @llvm.sqrt.f80(x86_fp80) #0

; Function Attrs: nounwind readnone speculatable
declare x86_fp80 @llvm.fabs.f80(x86_fp80) #0

; Function Attrs: nounwind readnone speculatable
declare x86_fp80 @llvm.cos.f80(x86_fp80) #0

; Function Attrs: nounwind readnone speculatable
declare x86_fp80 @llvm.sin.f80(x86_fp80) #0

declare i32 @__asm_wait(x86_fp80) local_unnamed_addr

declare i16 @__asm_fnstsw(i32) local_unnamed_addr

declare double @__decompiler_undefined_function_3() local_unnamed_addr

attributes #0 = { nounwind readnone speculatable }
