source_filename = "test"
target datalayout = "e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"

@st7 = internal unnamed_addr global x86_fp80 0xK00000000000000000000
@fpu_stat_TOP = internal unnamed_addr global i3 0
@fpsw = internal unnamed_addr global i32 0
@eax = internal unnamed_addr global i32 0, align 8
@ecx = internal unnamed_addr global i32 0, align 8
@edx = internal unnamed_addr global i32 0, align 8
@ebx = internal unnamed_addr global i32 0
@esi = internal unnamed_addr global i32 0
@0 = external global i32

define i32 @function_0(i32 %arg1) local_unnamed_addr {
dec_label_pc_0:
  %fpu_stat_TOP.global-to-local = alloca i3, align 1
  %st4.global-to-local = alloca x86_fp80, align 4
  %st5.global-to-local = alloca x86_fp80, align 4
  %st6.global-to-local = alloca x86_fp80, align 4
  %st7.global-to-local = alloca x86_fp80, align 4
  %v0_5 = load i32, i32* @eax, align 8
  store i32 %v0_5, i32* @ebx, align 4
  %v1_a = add i32 %arg1, 48
  %v2_a = inttoptr i32 %v1_a to i32*
  %v3_a = load i32, i32* %v2_a, align 4
  store i32 %v3_a, i32* @esi, align 4
  %v0_d = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v3_d = load double, double* bitcast (i32* @ecx to double*), align 8
  %tmp245 = call double @llvm.fabs.f64(double %v3_d)
  %v2_f = fpext double %tmp245 to x86_fp80
  store x86_fp80 %v2_f, x86_fp80* %st7.global-to-local, align 4
  %v3_11 = load double, double* bitcast (i32* @edx to double*), align 8
  %tmp246 = call double @llvm.fabs.f64(double %v3_11)
  %v2_13 = fpext double %tmp246 to x86_fp80
  store x86_fp80 %v2_13, x86_fp80* %st6.global-to-local, align 4
  %v3_15 = load double, double* bitcast (i32* @eax to double*), align 8
  %v4_15 = fpext double %v3_15 to x86_fp80
  %v2_17 = call x86_fp80 @llvm.fabs.f80(x86_fp80 %v4_15)
  store x86_fp80 %v2_17, x86_fp80* %st5.global-to-local, align 4
  %v2_19 = xor i3 %v0_d, -4
  %v3_1b = fmul x86_fp80 %v4_15, %v4_15
  %v3_1f = fmul x86_fp80 %v2_13, %v2_13
  %v4_21 = fadd x86_fp80 %v3_1f, %v3_1b
  %v3_25 = fmul x86_fp80 %v2_f, %v2_f
  %v4_27 = fadd x86_fp80 %v3_25, %v4_21
  store x86_fp80 %v4_27, x86_fp80* %st4.global-to-local, align 4
  store i3 %v2_19, i3* %fpu_stat_TOP.global-to-local, align 1
  %v0_32 = load i32, i32* @fpsw, align 4
  %v1_32 = call i16 @__asm_fnstsw(i32 %v0_32)
  %v2_32 = sext i16 %v1_32 to i32
  %v3_32 = load i32, i32* @eax, align 8
  %v4_32 = and i32 %v3_32, -65536
  %tmp249 = udiv i32 %v2_32, 2
  %v12_34 = and i32 %tmp249, 32512
  %v2_32.masked = and i32 %v2_32, -65281
  %v13_34 = or i32 %v4_32, %v2_32.masked
  %v14_34 = or i32 %v13_34, %v12_34
  store i32 %v14_34, i32* @eax, align 8
  %v15_3410 = and i32 %v2_32, 256
  %v16_34 = icmp ne i32 %v15_3410, 0
  %v1_36 = icmp eq i1 %v16_34, false
  %v0_45 = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  br i1 %v1_36, label %dec_label_pc_45, label %dec_label_pc_38

dec_label_pc_38:                                  ; preds = %dec_label_pc_0
  %v4_3c = add i3 %v0_45, 1
  store i3 %v4_3c, i3* %fpu_stat_TOP.global-to-local, align 1
  br label %dec_label_pc_61

dec_label_pc_45:                                  ; preds = %dec_label_pc_0
  %v0_4d = load i32, i32* @fpsw, align 4
  %v1_4d = call i16 @__asm_fnstsw(i32 %v0_4d)
  %v2_4d = sext i16 %v1_4d to i32
  %v3_4d = load i32, i32* @eax, align 8
  %v4_4d = and i32 %v3_4d, -65536
  %v4_4f3 = udiv i32 %v2_4d, 512
  %tmp248 = trunc i32 %v4_4f3 to i8
  %tmp250 = urem i8 %tmp248, -128
  %v5_4f = icmp eq i8 %tmp250, 0
  %v10_4f = zext i8 %tmp250 to i32
  %v12_4f = mul i32 %v10_4f, 256
  %v2_4d.masked = and i32 %v2_4d, -65281
  %v13_4f = or i32 %v4_4d, %v2_4d.masked
  %v14_4f = or i32 %v13_4f, %v12_4f
  store i32 %v14_4f, i32* @eax, align 8
  %v15_4f11 = and i32 %v2_4d, 256
  %v16_4f = icmp ne i32 %v15_4f11, 0
  %v2_51 = or i1 %v16_4f, %v5_4f
  br i1 %v2_51, label %dec_label_pc_59, label %dec_label_pc_53

dec_label_pc_53:                                  ; preds = %dec_label_pc_45
  %v0_53 = call x86_fp80 @function_6f()
  store x86_fp80 %v0_53, x86_fp80* %st7.global-to-local, align 4
  %v1_53 = fptrunc x86_fp80 %v0_53 to float
  %v2_53 = bitcast float %v1_53 to i32
  store i32 %v2_53, i32* @eax, align 8
  br label %dec_label_pc_59

dec_label_pc_59:                                  ; preds = %dec_label_pc_53, %dec_label_pc_45
  %v0_59 = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v1_59 = load i32, i32* @esi, align 4
  %v2_59 = add i32 %v1_59, -72
  %v3_59 = inttoptr i32 %v2_59 to double*
  %v4_59 = load double, double* %v3_59, align 4
  %v5_59 = fpext double %v4_59 to x86_fp80
  %v6_59 = add i3 %v0_59, -1
  store i3 %v6_59, i3* %fpu_stat_TOP.global-to-local, align 1
  %v3_5c = add i32 %v1_59, -88
  %v4_5c = inttoptr i32 %v3_5c to double*
  %v5_5c = load double, double* %v4_5c, align 4
  %v6_5c = fpext double %v5_5c to x86_fp80
  %v7_5c = fmul x86_fp80 %v5_59, %v6_5c
  %v3_5f = load x86_fp80, x86_fp80* %st4.global-to-local, align 4
  %v4_5f = fdiv x86_fp80 %v7_5c, %v3_5f
  br label %dec_label_pc_61

dec_label_pc_61:                                  ; preds = %dec_label_pc_59, %dec_label_pc_38
  %storemerge12 = phi x86_fp80 [ 0xK3FFF8000000000000000, %dec_label_pc_38 ], [ %v4_5f, %dec_label_pc_59 ]
  %storemerge = phi i3 [ %v0_45, %dec_label_pc_38 ], [ %v0_59, %dec_label_pc_59 ]
  store i3 %storemerge, i3* @fpu_stat_TOP, align 1
  %v3_61 = load x86_fp80, x86_fp80* %st5.global-to-local, align 4
  store x86_fp80 %storemerge12, x86_fp80* %st5.global-to-local, align 4
  %v4_63 = fmul x86_fp80 %storemerge12, %v3_61
  %v3_65 = load x86_fp80, x86_fp80* %st6.global-to-local, align 4
  store x86_fp80 %v4_63, x86_fp80* %st6.global-to-local, align 4
  %v4_67 = fmul x86_fp80 %storemerge12, %v3_65
  %v3_69 = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  store x86_fp80 %v4_67, x86_fp80* @st7, align 4
  %v4_6b = fmul x86_fp80 %storemerge12, %v3_69
  store x86_fp80 %v4_6b, x86_fp80* %st4.global-to-local, align 4
  %v3_6d = call i32 @function_78(i32 ptrtoint (i32* @0 to i32), i32 ptrtoint (i32* @0 to i32), i32 ptrtoint (i32* @0 to i32))
  store i32 %v3_6d, i32* @eax, align 8
  ret i32 %v3_6d
}

define x86_fp80 @function_6f() local_unnamed_addr {
dec_label_pc_6f:
  %v1_71 = load i32, i32* @esi, align 4
  %v2_71 = add i32 %v1_71, -80
  %v3_71 = inttoptr i32 %v2_71 to double*
  %v4_71 = load double, double* %v3_71, align 4
  %v5_71 = fpext double %v4_71 to x86_fp80
  %v3_74 = add i32 %v1_71, -88
  %v4_74 = inttoptr i32 %v3_74 to double*
  %v5_74 = load double, double* %v4_74, align 4
  %v6_74 = fpext double %v5_74 to x86_fp80
  %v7_74 = fmul x86_fp80 %v5_71, %v6_74
  ret x86_fp80 %v7_74
}

define i32 @function_78(i32 %arg1, i32 %arg2, i32 %arg3) local_unnamed_addr {
dec_label_pc_78:
  %fpu_stat_TOP.global-to-local = alloca i3, align 1
  %st7.global-to-local = alloca x86_fp80, align 4
  %v0_78 = load i3, i3* @fpu_stat_TOP, align 1
  %v5_78 = add i3 %v0_78, 1
  store i3 %v5_78, i3* %fpu_stat_TOP.global-to-local, align 1
  %v0_7c = load i32, i32* @fpsw, align 4
  %v1_7c = call i16 @__asm_fnstsw(i32 %v0_7c)
  %v2_7c = sext i16 %v1_7c to i32
  %v3_7c = load i32, i32* @eax, align 8
  %v4_7c = and i32 %v3_7c, -65536
  %tmp73 = udiv i32 %v2_7c, 2
  %v12_7e = and i32 %tmp73, 32512
  %v2_7c.masked = and i32 %v2_7c, -65281
  %v13_7e = or i32 %v4_7c, %v2_7c.masked
  %v14_7e = or i32 %v13_7e, %v12_7e
  store i32 %v14_7e, i32* @eax, align 8
  %v0_86 = load i32, i32* @fpsw, align 4
  %v1_86 = call i16 @__asm_fnstsw(i32 %v0_86)
  %v2_86 = sext i16 %v1_86 to i32
  %v3_86 = load i32, i32* @eax, align 8
  %v4_86 = and i32 %v3_86, -65536
  %tmp74 = udiv i32 %v2_86, 2
  %v12_88 = and i32 %tmp74, 32512
  %v2_86.masked = and i32 %v2_86, -65281
  %v13_88 = or i32 %v4_86, %v2_86.masked
  %v14_88 = or i32 %v13_88, %v12_88
  store i32 %v14_88, i32* @eax, align 8
  %v0_92 = load i32, i32* @fpsw, align 4
  %v1_92 = call i16 @__asm_fnstsw(i32 %v0_92)
  %v2_92 = sext i16 %v1_92 to i32
  %v3_92 = load i32, i32* @eax, align 8
  %v4_92 = and i32 %v3_92, -65536
  %tmp75 = udiv i32 %v2_92, 2
  %v12_94 = and i32 %tmp75, 32512
  %v2_92.masked = and i32 %v2_92, -65281
  %v13_94 = or i32 %v4_92, %v2_92.masked
  %v14_94 = or i32 %v13_94, %v12_94
  store i32 %v14_94, i32* @eax, align 8
  %v1_9b = load x86_fp80, x86_fp80* @st7, align 4
  %v2_9b = load i32, i32* @esi, align 4
  %v3_9b = add i32 %v2_9b, -56
  %v4_9b = inttoptr i32 %v3_9b to double*
  %v5_9b = load double, double* %v4_9b, align 4
  %v6_9b = fpext double %v5_9b to x86_fp80
  %v7_9b = fadd x86_fp80 %v1_9b, %v6_9b
  store x86_fp80 %v7_9b, x86_fp80* %st7.global-to-local, align 4
  %v3_a0 = add i32 %v2_9b, -48
  %v4_a0 = inttoptr i32 %v3_a0 to double*
  %v5_a0 = load double, double* %v4_a0, align 4
  %v6_a0 = fpext double %v5_a0 to x86_fp80
  %v7_a0 = fadd x86_fp80 %v7_9b, %v6_a0
  store x86_fp80 %v7_a0, x86_fp80* %st7.global-to-local, align 4
  %v3_a5 = add i32 %v2_9b, -64
  %v4_a5 = inttoptr i32 %v3_a5 to double*
  %v5_a5 = load double, double* %v4_a5, align 4
  %v6_a5 = fpext double %v5_a5 to x86_fp80
  %v7_a5 = fadd x86_fp80 %v7_a0, %v6_a5
  store x86_fp80 %v7_a5, x86_fp80* %st7.global-to-local, align 4
  %v0_ac = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v2_ac = add i3 %v0_ac, -1
  store i3 %v2_ac, i3* %fpu_stat_TOP.global-to-local, align 1
  %v0_c0 = load i32, i32* @fpsw, align 4
  %v1_c0 = call i16 @__asm_fnstsw(i32 %v0_c0)
  %v2_c0 = sext i16 %v1_c0 to i32
  %v3_c0 = load i32, i32* @eax, align 8
  %v4_c0 = and i32 %v3_c0, -65536
  %v4_c27 = udiv i32 %v2_c0, 512
  %tmp68 = trunc i32 %v4_c27 to i8
  %tmp79 = urem i8 %tmp68, -128
  %v5_c2 = icmp eq i8 %tmp79, 0
  %v10_c2 = zext i8 %tmp79 to i32
  %v12_c2 = mul i32 %v10_c2, 256
  %v2_c0.masked = and i32 %v2_c0, -65281
  %v13_c2 = or i32 %v4_c0, %v2_c0.masked
  %v14_c2 = or i32 %v13_c2, %v12_c2
  store i32 %v14_c2, i32* @eax, align 8
  %v15_c249 = and i32 %v2_c0, 256
  %v16_c2 = icmp ne i32 %v15_c249, 0
  %v2_c4 = or i1 %v16_c2, %v5_c2
  br i1 %v2_c4, label %dec_label_pc_ca, label %dec_label_pc_174

dec_label_pc_ca:                                  ; preds = %dec_label_pc_78
  %v0_cd = load i32, i32* @fpsw, align 4
  %v1_cd = call i16 @__asm_fnstsw(i32 %v0_cd)
  %v2_cd = sext i16 %v1_cd to i32
  %v3_cd = load i32, i32* @eax, align 8
  %v4_cd = and i32 %v3_cd, -65536
  %v4_cf9 = udiv i32 %v2_cd, 512
  %tmp69 = trunc i32 %v4_cf9 to i8
  %tmp80 = urem i8 %tmp69, -128
  %v5_cf = icmp eq i8 %tmp80, 0
  %v10_cf = zext i8 %tmp80 to i32
  %v12_cf = mul i32 %v10_cf, 256
  %v2_cd.masked = and i32 %v2_cd, -65281
  %v13_cf = or i32 %v4_cd, %v2_cd.masked
  %v14_cf = or i32 %v13_cf, %v12_cf
  store i32 %v14_cf, i32* @eax, align 8
  %v15_cf53 = and i32 %v2_cd, 256
  %v16_cf = icmp ne i32 %v15_cf53, 0
  %v2_d1 = or i1 %v16_cf, %v5_cf
  %v0_17e = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v1_183 = load i32, i32* @esi, align 4
  br i1 %v2_d1, label %dec_label_pc_17e, label %dec_label_pc_ca.dec_label_pc_dc_crit_edge

dec_label_pc_ca.dec_label_pc_dc_crit_edge:        ; preds = %dec_label_pc_ca
  %v3_df.pre = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  br label %dec_label_pc_dc

dec_label_pc_dc:                                  ; preds = %dec_label_pc_ca.dec_label_pc_dc_crit_edge, %dec_label_pc_17e
  %v3_df = phi x86_fp80 [ %v3_df.pre, %dec_label_pc_ca.dec_label_pc_dc_crit_edge ], [ %v5_183, %dec_label_pc_17e ]
  %v2_dc = add i32 %v1_183, -72
  %v3_dc = inttoptr i32 %v2_dc to double*
  %v4_dc = load double, double* %v3_dc, align 4
  %v5_dc = fpext double %v4_dc to x86_fp80
  %v6_dc = add i3 %v0_17e, -1
  store i3 %v6_dc, i3* %fpu_stat_TOP.global-to-local, align 1
  %v4_df = fdiv x86_fp80 %v5_dc, %v3_df
  br label %dec_label_pc_e1

dec_label_pc_e1:                                  ; preds = %dec_label_pc_174, %dec_label_pc_dc
  %v0_f6 = phi i32 [ %v2_e5.pre, %dec_label_pc_174 ], [ %v1_183, %dec_label_pc_dc ]
  %storemerge = phi x86_fp80 [ 0xK3FFF8000000000000000, %dec_label_pc_174 ], [ %v4_df, %dec_label_pc_dc ]
  %storemerge21 = phi i3 [ %v0_174, %dec_label_pc_174 ], [ %v0_17e, %dec_label_pc_dc ]
  store i3 %storemerge21, i3* %fpu_stat_TOP.global-to-local, align 1
  %v4_e3 = fmul x86_fp80 %storemerge, %storemerge
  store x86_fp80 %v4_e3, x86_fp80* %st7.global-to-local, align 4
  %v3_e5 = add i32 %v0_f6, -56
  %v4_e5 = inttoptr i32 %v3_e5 to double*
  %v5_e5 = load double, double* %v4_e5, align 4
  %v6_e5 = fpext double %v5_e5 to x86_fp80
  %v7_e5 = fsub x86_fp80 %v4_e3, %v6_e5
  %v4_ea = fmul x86_fp80 %v7_e5, %v7_e5
  store x86_fp80 %v4_ea, x86_fp80* %st7.global-to-local, align 4
  %v3_ec = add i32 %v0_f6, -48
  %v4_ec = inttoptr i32 %v3_ec to double*
  %v5_ec = load double, double* %v4_ec, align 4
  %v6_ec = fpext double %v5_ec to x86_fp80
  %v7_ec = fsub x86_fp80 %v4_ea, %v6_ec
  %v4_f1 = fmul x86_fp80 %v7_ec, %v7_ec
  store x86_fp80 %v4_f1, x86_fp80* %st7.global-to-local, align 4
  %v3_f3 = add i32 %v0_f6, -64
  %v4_f3 = inttoptr i32 %v3_f3 to double*
  %v5_f3 = load double, double* %v4_f3, align 4
  %v6_f3 = fpext double %v5_f3 to x86_fp80
  %v7_f3 = fsub x86_fp80 %v4_f1, %v6_f3
  store x86_fp80 %v7_f3, x86_fp80* %st7.global-to-local, align 4
  %v1_f6 = add i32 %v0_f6, -92
  %v2_f6 = inttoptr i32 %v1_f6 to i32*
  %v3_f6 = load i32, i32* %v2_f6, align 4
  %v10_f6 = icmp eq i32 %v3_f6, 0
  br i1 %v10_f6, label %dec_label_pc_130, label %dec_label_pc_100

dec_label_pc_100:                                 ; preds = %dec_label_pc_e1
  %v0_10b = load i32, i32* @fpsw, align 4
  %v1_10b = call i16 @__asm_fnstsw(i32 %v0_10b)
  %v2_10b = sext i16 %v1_10b to i32
  %v3_10b = load i32, i32* @eax, align 8
  %v4_10b = and i32 %v3_10b, -65536
  %tmp76 = udiv i32 %v2_10b, 2
  %v12_10d = and i32 %tmp76, 32512
  %v2_10b.masked = and i32 %v2_10b, -65281
  %v13_10d = or i32 %v4_10b, %v2_10b.masked
  %v14_10d = or i32 %v13_10d, %v12_10d
  store i32 %v14_10d, i32* @eax, align 8
  %v0_115 = load i32, i32* @fpsw, align 4
  %v1_115 = call i16 @__asm_fnstsw(i32 %v0_115)
  %v2_115 = sext i16 %v1_115 to i32
  %v3_115 = load i32, i32* @eax, align 8
  %v4_115 = and i32 %v3_115, -65536
  %tmp77 = udiv i32 %v2_115, 2
  %v12_117 = and i32 %tmp77, 32512
  %v2_115.masked = and i32 %v2_115, -65281
  %v13_117 = or i32 %v4_115, %v2_115.masked
  %v14_117 = or i32 %v13_117, %v12_117
  store i32 %v14_117, i32* @eax, align 8
  %v0_121 = load i32, i32* @fpsw, align 4
  %v1_121 = call i16 @__asm_fnstsw(i32 %v0_121)
  %v2_121 = sext i16 %v1_121 to i32
  %v3_121 = load i32, i32* @eax, align 8
  %v4_121 = and i32 %v3_121, -65536
  %tmp78 = udiv i32 %v2_121, 2
  %v12_123 = and i32 %tmp78, 32512
  %v2_121.masked = and i32 %v2_121, -65281
  %v13_123 = or i32 %v4_121, %v2_121.masked
  %v14_123 = or i32 %v13_123, %v12_123
  store i32 %v14_123, i32* @eax, align 8
  %storemerge44.in.in.pre = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v0_130.pre = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v1_132.pre = load i32, i32* @esi, align 4
  br label %dec_label_pc_130

dec_label_pc_130:                                 ; preds = %dec_label_pc_e1, %dec_label_pc_100
  %v2_159 = phi i32 [ %v0_f6, %dec_label_pc_e1 ], [ %v1_132.pre, %dec_label_pc_100 ]
  %v0_130 = phi i3 [ %storemerge21, %dec_label_pc_e1 ], [ %v0_130.pre, %dec_label_pc_100 ]
  %storemerge44.in.in = phi x86_fp80 [ %v7_f3, %dec_label_pc_e1 ], [ %storemerge44.in.in.pre, %dec_label_pc_100 ]
  store x86_fp80 %storemerge44.in.in, x86_fp80* %st7.global-to-local, align 4
  %v2_132 = add i32 %v2_159, -16
  %v3_132 = inttoptr i32 %v2_132 to double*
  %v4_132 = load double, double* %v3_132, align 4
  %v5_132 = fpext double %v4_132 to x86_fp80
  store x86_fp80 %v5_132, x86_fp80* %st7.global-to-local, align 4
  %v2_137 = load i32, i32* @ecx, align 8
  %v3_137 = add i32 %v2_137, 8
  %v4_137 = inttoptr i32 %v3_137 to double*
  %v5_137 = load double, double* %v4_137, align 4
  %v6_137 = fpext double %v5_137 to x86_fp80
  %v7_137 = fmul x86_fp80 %v5_132, %v6_137
  %v4_13a = fptrunc x86_fp80 %v7_137 to double
  store double %v4_13a, double* %v4_137, align 4
  %v2_13f = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v4_13f = fmul x86_fp80 %v2_13f, %v2_13f
  %v4_141 = fmul x86_fp80 %v4_13f, %v4_13f
  store x86_fp80 %v4_141, x86_fp80* %st7.global-to-local, align 4
  %v4_147 = fadd x86_fp80 %v4_141, 0xKBFFF8000000000000000
  %v3_14d = add i32 %v2_159, -24
  %v4_14d = inttoptr i32 %v3_14d to double*
  %v5_14d = load double, double* %v4_14d, align 4
  %v6_14d = fpext double %v5_14d to x86_fp80
  %v7_14d = fmul x86_fp80 %v4_147, %v6_14d
  %v4_150 = fsub x86_fp80 %v4_141, %v7_14d
  store x86_fp80 %v4_150, x86_fp80* %st7.global-to-local, align 4
  %v3_152 = add i32 %v2_159, -32
  %v4_152 = inttoptr i32 %v3_152 to double*
  %v5_152 = load double, double* %v4_152, align 4
  %v6_152 = fpext double %v5_152 to x86_fp80
  %v7_152 = fmul x86_fp80 %v4_147, %v6_152
  %v4_155 = fsub x86_fp80 %v4_150, %v7_152
  store x86_fp80 %v4_155, x86_fp80* %st7.global-to-local, align 4
  %v4_157 = fdiv x86_fp80 %v4_147, %v4_155
  %v3_159 = add i32 %v2_159, -40
  %v4_159 = inttoptr i32 %v3_159 to double*
  %v5_159 = load double, double* %v4_159, align 4
  %v6_159 = fpext double %v5_159 to x86_fp80
  %v7_159 = fmul x86_fp80 %v4_157, %v6_159
  %v4_15c = fsub x86_fp80 %v4_155, %v7_159
  %v2_160 = call x86_fp80 @llvm.fabs.f80(x86_fp80 %v4_15c)
  %v4_162 = fsub x86_fp80 %v2_160, %v2_160
  %v4_164 = fmul x86_fp80 %v4_162, %v4_162
  store x86_fp80 %v4_164, x86_fp80* %st7.global-to-local, align 4
  %v2_166 = load i32, i32* @edx, align 8
  %v3_166 = fptrunc x86_fp80 %v4_164 to double
  %v4_166 = inttoptr i32 %v2_166 to double*
  store double %v3_166, double* %v4_166, align 4
  %v1_168 = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v2_168 = load i32, i32* @ebx, align 4
  %v3_168 = fptrunc x86_fp80 %v1_168 to double
  %v4_168 = inttoptr i32 %v2_168 to double*
  store double %v3_168, double* %v4_168, align 4
  %v1_16a = load x86_fp80, x86_fp80* %st7.global-to-local, align 4
  %v2_16a = load i32, i32* @ecx, align 8
  %v3_16a = fptrunc x86_fp80 %v1_16a to double
  %v4_16a = inttoptr i32 %v2_16a to double*
  store double %v3_16a, double* %v4_16a, align 4
  %v5_16a = xor i3 %v0_130, -4
  store i3 %v5_16a, i3* %fpu_stat_TOP.global-to-local, align 1
  store i32 %v2_168, i32* @eax, align 8
  ret i32 %v2_168

dec_label_pc_174:                                 ; preds = %dec_label_pc_78
  %v0_174 = load i3, i3* %fpu_stat_TOP.global-to-local, align 1
  %v4_174 = add i3 %v0_174, 1
  store i3 %v4_174, i3* %fpu_stat_TOP.global-to-local, align 1
  %v2_e5.pre = load i32, i32* @esi, align 4
  br label %dec_label_pc_e1

dec_label_pc_17e:                                 ; preds = %dec_label_pc_ca
  %v2_183 = add i32 %v1_183, -80
  %v3_183 = inttoptr i32 %v2_183 to double*
  %v4_183 = load double, double* %v3_183, align 4
  %v5_183 = fpext double %v4_183 to x86_fp80
  store x86_fp80 %v5_183, x86_fp80* %st7.global-to-local, align 4
  br label %dec_label_pc_dc
}

; Function Attrs: nounwind readnone speculatable
declare x86_fp80 @llvm.fabs.f80(x86_fp80) #0

declare i16 @__asm_fnstsw(i32) local_unnamed_addr

; Function Attrs: nounwind readnone speculatable
declare double @llvm.fabs.f64(double) #0

attributes #0 = { nounwind readnone speculatable }
